Search

David M. Gray

Supervisory Patent Examiner (ID: 287, Phone: (571)272-2119 , Office: P/2852 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2853, 2602, 2101, 2852
Total Applications
2033
Issued Applications
1687
Pending Applications
28
Abandoned Applications
318

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17032873 [patent_doc_number] => 11094691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/736463 [patent_app_country] => US [patent_app_date] => 2020-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10553 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16736463 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/736463
Semiconductor device Jan 6, 2020 Issued
Array ( [id] => 15807587 [patent_doc_number] => 20200126936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => MANUFACTURING PROCESS FOR SEPARATING LOGIC AND MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 16/722278 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16722278 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/722278
Manufacturing process for separating logic and memory array Dec 19, 2019 Issued
Array ( [id] => 17464001 [patent_doc_number] => 20220077307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => TRENCH GATE IGBT AND DEVICE [patent_app_type] => utility [patent_app_number] => 17/417356 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2986 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17417356 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/417356
Trench gate IGBT and device Dec 16, 2019 Issued
Array ( [id] => 15775701 [patent_doc_number] => 20200118868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => CREATING AN ALIGNED VIA AND METAL LINE IN AN INTEGRATED CIRCUIT INCLUDING FORMING AN OVERSIZED VIA MASK [patent_app_type] => utility [patent_app_number] => 16/713044 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16713044 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/713044
Creating an aligned via and metal line in an integrated circuit including forming an oversized via mask Dec 12, 2019 Issued
Array ( [id] => 17574410 [patent_doc_number] => 11322685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Controlling positive feedback in filamentary RRAM structures [patent_app_type] => utility [patent_app_number] => 16/689987 [patent_app_country] => US [patent_app_date] => 2019-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 31 [patent_no_of_words] => 15524 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16689987 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/689987
Controlling positive feedback in filamentary RRAM structures Nov 19, 2019 Issued
Array ( [id] => 16850826 [patent_doc_number] => 20210151571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/689923 [patent_app_country] => US [patent_app_date] => 2019-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16689923 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/689923
Semiconductor structures and methods of forming the same Nov 19, 2019 Issued
Array ( [id] => 16911515 [patent_doc_number] => 11043565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Three-dimensional memory device with source contacts connected by an adhesion layer and methods for forming the same [patent_app_type] => utility [patent_app_number] => 16/689539 [patent_app_country] => US [patent_app_date] => 2019-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 11994 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16689539 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/689539
Three-dimensional memory device with source contacts connected by an adhesion layer and methods for forming the same Nov 19, 2019 Issued
Array ( [id] => 17048116 [patent_doc_number] => 11101306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Image sensing device [patent_app_type] => utility [patent_app_number] => 16/687304 [patent_app_country] => US [patent_app_date] => 2019-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5945 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16687304 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/687304
Image sensing device Nov 17, 2019 Issued
Array ( [id] => 17063211 [patent_doc_number] => 11107823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => Integrated structures and methods of forming integrated structures [patent_app_type] => utility [patent_app_number] => 16/684515 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6204 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684515 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684515
Integrated structures and methods of forming integrated structures Nov 13, 2019 Issued
Array ( [id] => 16820105 [patent_doc_number] => 11004944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Gate cut device fabrication with extended height gates [patent_app_type] => utility [patent_app_number] => 16/682361 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 4541 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682361 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/682361
Gate cut device fabrication with extended height gates Nov 12, 2019 Issued
Array ( [id] => 17301150 [patent_doc_number] => 20210396989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => METHODS FOR FORMING PATTERNED INSULATING LAYERS ON CONDUCTIVE LAYERS AND DEVICES MANUFACTURED USING SUCH METHODS [patent_app_type] => utility [patent_app_number] => 17/296913 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9533 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17296913 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/296913
METHODS FOR FORMING PATTERNED INSULATING LAYERS ON CONDUCTIVE LAYERS AND DEVICES MANUFACTURED USING SUCH METHODS Nov 11, 2019 Abandoned
Array ( [id] => 17092954 [patent_doc_number] => 11121152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Three-dimensional memory device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/679265 [patent_app_country] => US [patent_app_date] => 2019-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6626 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16679265 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/679265
Three-dimensional memory device and manufacturing method thereof Nov 9, 2019 Issued
Array ( [id] => 17181380 [patent_doc_number] => 11158629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Polarization circuit of a power component [patent_app_type] => utility [patent_app_number] => 16/667977 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 6427 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667977 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667977
Polarization circuit of a power component Oct 29, 2019 Issued
Array ( [id] => 15564789 [patent_doc_number] => 20200066806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => ARRAY SUBSTRATE AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/667926 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667926 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667926
Array substrate and display device Oct 29, 2019 Issued
Array ( [id] => 16928488 [patent_doc_number] => 11049980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Integrated MIM diode [patent_app_type] => utility [patent_app_number] => 16/668004 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 40 [patent_no_of_words] => 10568 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16668004 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/668004
Integrated MIM diode Oct 29, 2019 Issued
Array ( [id] => 16456278 [patent_doc_number] => 20200365704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 16/667947 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9098 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667947 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667947
Semiconductor devices Oct 29, 2019 Issued
Array ( [id] => 17152636 [patent_doc_number] => 11145727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Semiconductor structure and method of forming the same [patent_app_type] => utility [patent_app_number] => 16/667893 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3017 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667893 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667893
Semiconductor structure and method of forming the same Oct 28, 2019 Issued
Array ( [id] => 16796173 [patent_doc_number] => 20210125990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => THIN FILM TRANSISTOR BASED MEMORY CELLS ON BOTH SIDES OF A LAYER OF LOGIC DEVICES [patent_app_type] => utility [patent_app_number] => 16/667740 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19245 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667740 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667740
Thin film transistor based memory cells on both sides of a layer of logic devices Oct 28, 2019 Issued
Array ( [id] => 16731245 [patent_doc_number] => 20210098393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => SYSTEMS AND METHODS FOR ELECTRICAL CHARGE DISSIPATION [patent_app_type] => utility [patent_app_number] => 16/662041 [patent_app_country] => US [patent_app_date] => 2019-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4378 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16662041 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/662041
SYSTEMS AND METHODS FOR ELECTRICAL CHARGE DISSIPATION Oct 23, 2019 Abandoned
Array ( [id] => 16796309 [patent_doc_number] => 20210126126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => SEMICONDUCTOR DEVICE WITH DOPED REGION ADJACENT ISOLATION STRUCTURE IN EXTENSION REGION [patent_app_type] => utility [patent_app_number] => 16/662276 [patent_app_country] => US [patent_app_date] => 2019-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16662276 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/662276
Semiconductor device with doped region adjacent isolation structure in extension region Oct 23, 2019 Issued
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