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David M. Mitchell

Examiner (ID: 18472)

Most Active Art Unit
3106
Art Unit(s)
3104, 3612, 3102, 3106
Total Applications
820
Issued Applications
743
Pending Applications
2
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10873205 [patent_doc_number] => 08898424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Memory address translation' [patent_app_type] => utility [patent_app_number] => 13/859502 [patent_app_country] => US [patent_app_date] => 2013-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5622 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13859502 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/859502
Memory address translation Apr 8, 2013 Issued
Array ( [id] => 10873205 [patent_doc_number] => 08898424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Memory address translation' [patent_app_type] => utility [patent_app_number] => 13/859502 [patent_app_country] => US [patent_app_date] => 2013-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5622 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13859502 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/859502
Memory address translation Apr 8, 2013 Issued
Array ( [id] => 9926229 [patent_doc_number] => 08984214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'Memory cell operation' [patent_app_type] => utility [patent_app_number] => 13/827135 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 11582 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13827135 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/827135
Memory cell operation Mar 13, 2013 Issued
Array ( [id] => 9992582 [patent_doc_number] => 09037803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-19 [patent_title] => 'Randomized page weights for optimizing buffer pool page reuse' [patent_app_type] => utility [patent_app_number] => 13/787501 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7018 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13787501 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/787501
Randomized page weights for optimizing buffer pool page reuse Mar 5, 2013 Issued
Array ( [id] => 8929762 [patent_doc_number] => 20130185522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => 'ALLOCATION AND WRITE POLICY FOR A GLUELESS AREA-EFFICIENT DIRECTORY CACHE FOR HOTLY CONTESTED CACHE LINES' [patent_app_type] => utility [patent_app_number] => 13/786305 [patent_app_country] => US [patent_app_date] => 2013-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6043 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13786305 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/786305
Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines Mar 4, 2013 Issued
Array ( [id] => 9644962 [patent_doc_number] => 20140223075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'PHYSICAL-TO-LOGICAL ADDRESS MAP TO SPEED UP A RECYCLE OPERATION IN A SOLID STATE DRIVE' [patent_app_type] => utility [patent_app_number] => 13/780229 [patent_app_country] => US [patent_app_date] => 2013-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2496 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13780229 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/780229
Physical-to-logical address map to speed up a recycle operation in a solid state drive Feb 27, 2013 Issued
Array ( [id] => 9398364 [patent_doc_number] => 20140095770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'Selective Protection of Lower Page Data During Upper Page Write' [patent_app_type] => utility [patent_app_number] => 13/781204 [patent_app_country] => US [patent_app_date] => 2013-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7871 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13781204 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/781204
Selective protection of lower page data during upper page write Feb 27, 2013 Issued
Array ( [id] => 10015150 [patent_doc_number] => 09058162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-16 [patent_title] => 'Storage control apparatus, storage apparatus, information processing system and processing method therefor' [patent_app_type] => utility [patent_app_number] => 13/780774 [patent_app_country] => US [patent_app_date] => 2013-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 17507 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13780774 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/780774
Storage control apparatus, storage apparatus, information processing system and processing method therefor Feb 27, 2013 Issued
Array ( [id] => 10137615 [patent_doc_number] => 09170935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-27 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/779603 [patent_app_country] => US [patent_app_date] => 2013-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 7667 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13779603 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/779603
Semiconductor memory device Feb 26, 2013 Issued
Array ( [id] => 10065704 [patent_doc_number] => 09104552 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-08-11 [patent_title] => 'Method for the use of shadow ghost lists to prevent excessive wear on FLASH based cache devices' [patent_app_type] => utility [patent_app_number] => 13/775214 [patent_app_country] => US [patent_app_date] => 2013-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3077 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13775214 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/775214
Method for the use of shadow ghost lists to prevent excessive wear on FLASH based cache devices Feb 23, 2013 Issued
Array ( [id] => 9688162 [patent_doc_number] => 20140244927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'STORAGE SYSTEM AND A METHOD FOR ALLOCATING DISK DRIVES TO REDUNDANCY ARRAY OF INDEPENDENT DISKS' [patent_app_type] => utility [patent_app_number] => 13/775199 [patent_app_country] => US [patent_app_date] => 2013-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11599 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13775199 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/775199
Storage system and a method for allocating disk drives to redundancy array of independent disks Feb 23, 2013 Issued
Array ( [id] => 10150862 [patent_doc_number] => 09183153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-10 [patent_title] => 'Method and system for managing power grid data' [patent_app_type] => utility [patent_app_number] => 13/773816 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5506 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13773816 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/773816
Method and system for managing power grid data Feb 21, 2013 Issued
Array ( [id] => 10543573 [patent_doc_number] => 09268705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-23 [patent_title] => 'Data storage device and method of managing a cache in a data storage device' [patent_app_type] => utility [patent_app_number] => 13/773942 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7448 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13773942 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/773942
Data storage device and method of managing a cache in a data storage device Feb 21, 2013 Issued
Array ( [id] => 9563658 [patent_doc_number] => 20140181371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'METHOD AND SYSTEM FOR REDUCING MAPPING TABLE SIZE IN A STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 13/773946 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13773946 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/773946
Method and system for reducing mapping table size in a storage device Feb 21, 2013 Issued
Array ( [id] => 10137614 [patent_doc_number] => 09170934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-27 [patent_title] => 'Server and drive control device' [patent_app_type] => utility [patent_app_number] => 13/774016 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5886 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13774016 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/774016
Server and drive control device Feb 21, 2013 Issued
Array ( [id] => 10124356 [patent_doc_number] => 09158715 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-10-13 [patent_title] => 'Multi-input memory command prioritization' [patent_app_type] => utility [patent_app_number] => 13/773930 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3690 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13773930 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/773930
Multi-input memory command prioritization Feb 21, 2013 Issued
Array ( [id] => 9006104 [patent_doc_number] => 20130227229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'SEMICONDUCTOR DEVICE THAT BURST-OUTPUTS READ DATA' [patent_app_type] => utility [patent_app_number] => 13/773502 [patent_app_country] => US [patent_app_date] => 2013-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13006 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13773502 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/773502
SEMICONDUCTOR DEVICE THAT BURST-OUTPUTS READ DATA Feb 20, 2013 Abandoned
Array ( [id] => 8855423 [patent_doc_number] => 20130145098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'MEMORY PREFETCH SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/751502 [patent_app_country] => US [patent_app_date] => 2013-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5669 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13751502 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/751502
Memory prefetch systems and methods Jan 27, 2013 Issued
Array ( [id] => 9540042 [patent_doc_number] => 20140164689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-12 [patent_title] => 'SYSTEM AND METHOD FOR MANAGING PERFORMANCE OF A COMPUTING DEVICE HAVING DISSIMILAR MEMORY TYPES' [patent_app_type] => utility [patent_app_number] => 13/726537 [patent_app_country] => US [patent_app_date] => 2012-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5112 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13726537 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/726537
System and method for managing performance of a computing device having dissimilar memory types Dec 23, 2012 Issued
Array ( [id] => 10091999 [patent_doc_number] => 09128824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-08 [patent_title] => 'In-place change between transient and persistent state for data structures on non-volatile memory' [patent_app_type] => utility [patent_app_number] => 13/726303 [patent_app_country] => US [patent_app_date] => 2012-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4537 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13726303 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/726303
In-place change between transient and persistent state for data structures on non-volatile memory Dec 23, 2012 Issued
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