
David M. Mitchell
Examiner (ID: 18472)
| Most Active Art Unit | 3106 |
| Art Unit(s) | 3104, 3612, 3102, 3106 |
| Total Applications | 820 |
| Issued Applications | 743 |
| Pending Applications | 2 |
| Abandoned Applications | 75 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9169720
[patent_doc_number] => 08595413
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-11-26
[patent_title] => 'Memory control method and device, memory access control method, computer program, and recording medium'
[patent_app_type] => utility
[patent_app_number] => 12/867584
[patent_app_country] => US
[patent_app_date] => 2008-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 42
[patent_no_of_words] => 26726
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[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12867584
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/867584 | Memory control method and device, memory access control method, computer program, and recording medium | Dec 8, 2008 | Issued |
Array
(
[id] => 9940680
[patent_doc_number] => 08990511
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-03-24
[patent_title] => 'Multiprocessor, cache synchronization control method and program therefor'
[patent_app_type] => utility
[patent_app_number] => 12/734421
[patent_app_country] => US
[patent_app_date] => 2008-10-31
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12734421
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/734421 | Multiprocessor, cache synchronization control method and program therefor | Oct 30, 2008 | Issued |
Array
(
[id] => 4636895
[patent_doc_number] => 08015358
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-09-06
[patent_title] => 'System bus structure for large L2 cache array topology with different latency domains'
[patent_app_type] => utility
[patent_app_number] => 12/207393
[patent_app_country] => US
[patent_app_date] => 2008-09-09
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/08/015/08015358.pdf
[firstpage_image] =>[orig_patent_app_number] => 12207393
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/207393 | System bus structure for large L2 cache array topology with different latency domains | Sep 8, 2008 | Issued |
Array
(
[id] => 37478
[patent_doc_number] => 07793048
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-07
[patent_title] => 'System bus structure for large L2 cache array topology with different latency domains'
[patent_app_type] => utility
[patent_app_number] => 12/207445
[patent_app_country] => US
[patent_app_date] => 2008-09-09
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[pdf_file] => patents/07/793/07793048.pdf
[firstpage_image] =>[orig_patent_app_number] => 12207445
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/207445 | System bus structure for large L2 cache array topology with different latency domains | Sep 8, 2008 | Issued |
Array
(
[id] => 4712851
[patent_doc_number] => 20080301377
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[patent_kind] => A1
[patent_issue_date] => 2008-12-04
[patent_title] => 'DATA PROCESSING SYSTEM, CACHE SYSTEM AND METHOD FOR UPDATING AN INVALID COHERENCY STATE IN RESPONSE TO SNOOPING AN OPERATION'
[patent_app_type] => utility
[patent_app_number] => 12/190766
[patent_app_country] => US
[patent_app_date] => 2008-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[pdf_file] => publications/A1/0301/20080301377.pdf
[firstpage_image] =>[orig_patent_app_number] => 12190766
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/190766 | Updating an invalid coherency state in response to snooping an operation | Aug 12, 2008 | Issued |
Array
(
[id] => 4585655
[patent_doc_number] => 07856525
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-12-21
[patent_title] => 'Content addressed storage device configured to maintain content address mapping'
[patent_app_type] => utility
[patent_app_number] => 12/217061
[patent_app_country] => US
[patent_app_date] => 2008-06-30
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[pdf_file] => patents/07/856/07856525.pdf
[firstpage_image] =>[orig_patent_app_number] => 12217061
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/217061 | Content addressed storage device configured to maintain content address mapping | Jun 29, 2008 | Issued |
Array
(
[id] => 4888940
[patent_doc_number] => 20080263272
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-23
[patent_title] => 'DATA STORAGE MANAGEMENT METHOD'
[patent_app_type] => utility
[patent_app_number] => 12/144742
[patent_app_country] => US
[patent_app_date] => 2008-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2803
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[pdf_file] => publications/A1/0263/20080263272.pdf
[firstpage_image] =>[orig_patent_app_number] => 12144742
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/144742 | Data storage management method for selectively controlling reutilization of space in a virtual tape system | Jun 23, 2008 | Issued |
Array
(
[id] => 4722169
[patent_doc_number] => 20080244121
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-02
[patent_title] => 'METHOD AND APPARATUS FOR MEMORY COMPRESSION'
[patent_app_type] => utility
[patent_app_number] => 12/131904
[patent_app_country] => US
[patent_app_date] => 2008-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
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[patent_no_of_words] => 17194
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[pdf_file] => publications/A1/0244/20080244121.pdf
[firstpage_image] =>[orig_patent_app_number] => 12131904
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/131904 | METHOD AND APPARATUS FOR MEMORY COMPRESSION | Jun 1, 2008 | Abandoned |
Array
(
[id] => 4472188
[patent_doc_number] => 07937555
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-03
[patent_title] => 'Data processing system and computer program product to allow PCI host bridge (PHB) to handle pre-fetch read transactions on the PCI bus which access system memory through translation control entry (TCE) table'
[patent_app_type] => utility
[patent_app_number] => 12/105113
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[patent_app_date] => 2008-04-17
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[pdf_file] => patents/07/937/07937555.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/105113 | Data processing system and computer program product to allow PCI host bridge (PHB) to handle pre-fetch read transactions on the PCI bus which access system memory through translation control entry (TCE) table | Apr 16, 2008 | Issued |
Array
(
[id] => 4678190
[patent_doc_number] => 20080215821
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-04
[patent_title] => 'DATA PROCESSING SYSTEM AND METHOD FOR EFFICIENT COMMUNICATION UTILIZING AN IN COHERENCY STATE'
[patent_app_type] => utility
[patent_app_number] => 12/103564
[patent_app_country] => US
[patent_app_date] => 2008-04-15
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[pdf_file] => publications/A1/0215/20080215821.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/103564 | Data processing system and method for efficient communication utilizing an in coherency state | Apr 14, 2008 | Issued |
Array
(
[id] => 4678184
[patent_doc_number] => 20080215815
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[patent_issue_date] => 2008-09-04
[patent_title] => 'SYSTEM AND METHOD OF IMPROVING TASK SWITCHING AND PAGE TRANSLATION PERFORMANCE UTILIZING A MULTILEVEL TRANSLATION LOOKASIDE BUFFER'
[patent_app_type] => utility
[patent_app_number] => 12/101728
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[patent_app_date] => 2008-04-11
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[firstpage_image] =>[orig_patent_app_number] => 12101728
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/101728 | System and method of improving task switching and page translation performance utilizing a multilevel translation lookaside buffer | Apr 10, 2008 | Issued |
Array
(
[id] => 4847553
[patent_doc_number] => 20080183961
[patent_country] => US
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[patent_issue_date] => 2008-07-31
[patent_title] => 'DISTRIBUTED RAID AND LOCATION INDEPENDENT CACHING SYSTEM'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/052410 | DISTRIBUTED RAID AND LOCATION INDEPENDENT CACHING SYSTEM | Mar 19, 2008 | Abandoned |
Array
(
[id] => 7542846
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[patent_issue_date] => 2011-11-15
[patent_title] => 'System and method for proxying data access commands in a clustered storage system'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/033985 | System and method for proxying data access commands in a clustered storage system | Feb 19, 2008 | Issued |
Array
(
[id] => 5381353
[patent_doc_number] => 20090193192
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[patent_issue_date] => 2009-07-30
[patent_title] => 'Method and Process for Expediting the Return of Line Exclusivity to a Given Processor Through Enhanced Inter-node Communications'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/021378 | Method and process for expediting the return of line exclusivity to a given processor through enhanced inter-node communications | Jan 28, 2008 | Issued |
Array
(
[id] => 7517814
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[patent_title] => 'Translation table coherency mecahanism using cache way and set index write buffers'
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[pdf_file] => patents/08/041/08041895.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/020698 | Translation table coherency mecahanism using cache way and set index write buffers | Jan 27, 2008 | Issued |
Array
(
[id] => 7972043
[patent_doc_number] => 07941599
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-10
[patent_title] => 'IT automation appliance imaging system and method'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/021143 | IT automation appliance imaging system and method | Jan 27, 2008 | Issued |
Array
(
[id] => 7557420
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[patent_issue_date] => 2011-11-29
[patent_title] => 'Internally triggered reconfiguration of programmable logic devices'
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Array
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Array
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[patent_title] => 'Virtual Processor Based Security For On-Chip Memory, and Applications Thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/021110 | Virtual processor based security for on-chip memory, and applications thereof | Jan 27, 2008 | Issued |
Array
(
[id] => 5381376
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[patent_country] => US
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[patent_issue_date] => 2009-07-30
[patent_title] => 'ERASING AND RESTORING FACTORY SETTINGS IN COMPUTER SYSTEMS'
[patent_app_type] => utility
[patent_app_number] => 12/020408
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/020408 | ERASING AND RESTORING FACTORY SETTINGS IN COMPUTER SYSTEMS | Jan 24, 2008 | Abandoned |