Search

David M. Mitchell

Examiner (ID: 18472)

Most Active Art Unit
3106
Art Unit(s)
3104, 3612, 3102, 3106
Total Applications
820
Issued Applications
743
Pending Applications
2
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5064781 [patent_doc_number] => 20070226423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Processor, data processing system, and method for initializing a memory block in a data processing system having multiple coherency domains' [patent_app_type] => utility [patent_app_number] => 11/388001 [patent_app_country] => US [patent_app_date] => 2006-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11959 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20070226423.pdf [firstpage_image] =>[orig_patent_app_number] => 11388001 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/388001
Processor, data processing system, and method for initializing a memory block in a data processing system having multiple coherency domains Mar 22, 2006 Issued
Array ( [id] => 5122026 [patent_doc_number] => 20070143741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Efficient per-object operations in software transactional memory' [patent_app_type] => utility [patent_app_number] => 11/389360 [patent_app_country] => US [patent_app_date] => 2006-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 18846 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20070143741.pdf [firstpage_image] =>[orig_patent_app_number] => 11389360 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/389360
Efficient per-object operations in software transactional memory Mar 22, 2006 Issued
Array ( [id] => 5761701 [patent_doc_number] => 20060212646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'Semiconductor device having flash memory' [patent_app_type] => utility [patent_app_number] => 11/377434 [patent_app_country] => US [patent_app_date] => 2006-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4704 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20060212646.pdf [firstpage_image] =>[orig_patent_app_number] => 11377434 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/377434
Semiconductor device having flash memory with a data length table Mar 16, 2006 Issued
Array ( [id] => 4978992 [patent_doc_number] => 20070220227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Techniques for managing data within a data storage system utilizing a flash-based memory vault' [patent_app_type] => utility [patent_app_number] => 11/378722 [patent_app_country] => US [patent_app_date] => 2006-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4889 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20070220227.pdf [firstpage_image] =>[orig_patent_app_number] => 11378722 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/378722
Techniques for managing data within a data storage system utilizing a flash-based memory vault Mar 16, 2006 Issued
Array ( [id] => 4978976 [patent_doc_number] => 20070220211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Load when reservation lost instruction for performing cacheline polling' [patent_app_type] => utility [patent_app_number] => 11/377504 [patent_app_country] => US [patent_app_date] => 2006-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6607 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20070220211.pdf [firstpage_image] =>[orig_patent_app_number] => 11377504 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/377504
Load when reservation lost instruction for performing cacheline polling Mar 15, 2006 Issued
Array ( [id] => 258101 [patent_doc_number] => 07577788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-18 [patent_title] => 'Disk array apparatus and disk array apparatus control method' [patent_app_type] => utility [patent_app_number] => 11/376121 [patent_app_country] => US [patent_app_date] => 2006-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 12650 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/577/07577788.pdf [firstpage_image] =>[orig_patent_app_number] => 11376121 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/376121
Disk array apparatus and disk array apparatus control method Mar 15, 2006 Issued
Array ( [id] => 4653323 [patent_doc_number] => 20080040580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Microcontroller based flash memory digital controller system' [patent_app_type] => utility [patent_app_number] => 11/288509 [patent_app_country] => US [patent_app_date] => 2005-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3351 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20080040580.pdf [firstpage_image] =>[orig_patent_app_number] => 11288509 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/288509
Microcontroller based flash memory digital controller system Nov 27, 2005 Issued
Array ( [id] => 925046 [patent_doc_number] => 07320060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-15 [patent_title] => 'Method, apparatus, and computer readable medium for managing back-up' [patent_app_type] => utility [patent_app_number] => 11/281506 [patent_app_country] => US [patent_app_date] => 2005-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6619 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/320/07320060.pdf [firstpage_image] =>[orig_patent_app_number] => 11281506 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/281506
Method, apparatus, and computer readable medium for managing back-up Nov 17, 2005 Issued
Array ( [id] => 626374 [patent_doc_number] => 07139889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'Computer system' [patent_app_type] => utility [patent_app_number] => 11/281384 [patent_app_country] => US [patent_app_date] => 2005-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 9108 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/139/07139889.pdf [firstpage_image] =>[orig_patent_app_number] => 11281384 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/281384
Computer system Nov 17, 2005 Issued
Array ( [id] => 316851 [patent_doc_number] => 07526607 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-28 [patent_title] => 'Network acceleration and long-distance pattern detection using improved caching and disk mapping' [patent_app_type] => utility [patent_app_number] => 11/233357 [patent_app_country] => US [patent_app_date] => 2005-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9469 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/526/07526607.pdf [firstpage_image] =>[orig_patent_app_number] => 11233357 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/233357
Network acceleration and long-distance pattern detection using improved caching and disk mapping Sep 21, 2005 Issued
Array ( [id] => 188389 [patent_doc_number] => 07650466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Method and apparatus for managing cache partitioning using a dynamic boundary' [patent_app_type] => utility [patent_app_number] => 11/233575 [patent_app_country] => US [patent_app_date] => 2005-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 12 [patent_no_of_words] => 4355 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/650/07650466.pdf [firstpage_image] =>[orig_patent_app_number] => 11233575 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/233575
Method and apparatus for managing cache partitioning using a dynamic boundary Sep 20, 2005 Issued
Array ( [id] => 4510703 [patent_doc_number] => 07949835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Data processing apparatus and method for controlling access to memory' [patent_app_type] => utility [patent_app_number] => 11/230498 [patent_app_country] => US [patent_app_date] => 2005-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7628 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/949/07949835.pdf [firstpage_image] =>[orig_patent_app_number] => 11230498 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/230498
Data processing apparatus and method for controlling access to memory Sep 20, 2005 Issued
Array ( [id] => 97177 [patent_doc_number] => 07739443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'Memory controller, memory device and control method for the memory controller' [patent_app_type] => utility [patent_app_number] => 11/230600 [patent_app_country] => US [patent_app_date] => 2005-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7856 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/739/07739443.pdf [firstpage_image] =>[orig_patent_app_number] => 11230600 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/230600
Memory controller, memory device and control method for the memory controller Sep 20, 2005 Issued
Array ( [id] => 5638892 [patent_doc_number] => 20060069866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Disk array apparatus, disk array control method and computer program product therefor' [patent_app_type] => utility [patent_app_number] => 11/230534 [patent_app_country] => US [patent_app_date] => 2005-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4163 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20060069866.pdf [firstpage_image] =>[orig_patent_app_number] => 11230534 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/230534
Disk array apparatus, disk array control method and computer program product therefor Sep 20, 2005 Abandoned
Array ( [id] => 586386 [patent_doc_number] => 07467265 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-16 [patent_title] => 'System and method for block conflict resolution within consistency interval marker based replication' [patent_app_type] => utility [patent_app_number] => 11/231185 [patent_app_country] => US [patent_app_date] => 2005-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15550 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/467/07467265.pdf [firstpage_image] =>[orig_patent_app_number] => 11231185 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/231185
System and method for block conflict resolution within consistency interval marker based replication Sep 19, 2005 Issued
Array ( [id] => 7690069 [patent_doc_number] => 20070233964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Set-associative cache using cache line decay counts and set overflow' [patent_app_type] => utility [patent_app_number] => 11/230866 [patent_app_country] => US [patent_app_date] => 2005-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7116 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20070233964.pdf [firstpage_image] =>[orig_patent_app_number] => 11230866 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/230866
Set-associative cache using cache line decay counts and set overflow Sep 19, 2005 Issued
Array ( [id] => 27266 [patent_doc_number] => 07802054 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Apparatus and methods using invalidity indicators for buffered memory' [patent_app_type] => utility [patent_app_number] => 11/230994 [patent_app_country] => US [patent_app_date] => 2005-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4646 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/802/07802054.pdf [firstpage_image] =>[orig_patent_app_number] => 11230994 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/230994
Apparatus and methods using invalidity indicators for buffered memory Sep 19, 2005 Issued
Array ( [id] => 580970 [patent_doc_number] => 07472227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-30 [patent_title] => 'Invalidating multiple address cache entries' [patent_app_type] => utility [patent_app_number] => 11/201971 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5286 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/472/07472227.pdf [firstpage_image] =>[orig_patent_app_number] => 11201971 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/201971
Invalidating multiple address cache entries Aug 10, 2005 Issued
Array ( [id] => 5155926 [patent_doc_number] => 20070038809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Method and apparatus for aging data in a cache' [patent_app_type] => utility [patent_app_number] => 11/201642 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20070038809.pdf [firstpage_image] =>[orig_patent_app_number] => 11201642 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/201642
Method and apparatus for aging data in a cache Aug 10, 2005 Issued
Array ( [id] => 5155927 [patent_doc_number] => 20070038810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Optimizing cached access to stack storage' [patent_app_type] => utility [patent_app_number] => 11/202477 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4961 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20070038810.pdf [firstpage_image] =>[orig_patent_app_number] => 11202477 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/202477
Optimizing cached access to stack storage Aug 10, 2005 Issued
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