Search

David M Purol

Examiner (ID: 9451, Phone: (571)272-6833 , Office: P/3634 )

Most Active Art Unit
3634
Art Unit(s)
3623, 3509, 2899, 3505, 3634
Total Applications
2967
Issued Applications
2213
Pending Applications
74
Abandoned Applications
680

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14764823 [patent_doc_number] => 10393804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit [patent_app_type] => utility [patent_app_number] => 16/170479 [patent_app_country] => US [patent_app_date] => 2018-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4477 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16170479 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/170479
Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit Oct 24, 2018 Issued
Array ( [id] => 14427147 [patent_doc_number] => 10318377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Storing address of spare in failed memory location [patent_app_type] => utility [patent_app_number] => 16/029829 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6846 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16029829 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/029829
Storing address of spare in failed memory location Jul 8, 2018 Issued
Array ( [id] => 12713200 [patent_doc_number] => 20180129566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => OPTICAL DISC APPARATUS AND OPTICAL DISC PROVIDED WITH QUALITY ESTIMETOR FOR GENERATING QUALITY VALUE OF RECORDING QUALITY OF OPTICAL DISC [patent_app_type] => utility [patent_app_number] => 15/864161 [patent_app_country] => US [patent_app_date] => 2018-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15864161 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/864161
Optical disc apparatus for recording and reproducing data onto and from an optical disc based on an evaluation value Jan 7, 2018 Issued
Array ( [id] => 13226667 [patent_doc_number] => 10127109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Resiliency to memory failures in computer systems [patent_app_type] => utility [patent_app_number] => 15/625985 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9100 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15625985 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/625985
Resiliency to memory failures in computer systems Jun 15, 2017 Issued
Array ( [id] => 14457663 [patent_doc_number] => 10324792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Resiliency to memory failures in computer systems [patent_app_type] => utility [patent_app_number] => 15/625957 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9129 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15625957 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/625957
Resiliency to memory failures in computer systems Jun 15, 2017 Issued
Array ( [id] => 11960163 [patent_doc_number] => 20170264316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'APPARATUS AND METHOD FOR RECEIVING SIGNAL IN COMMUNICATION SYSTEM SUPPORTING LOW DENSITY PARITY CHECK CODE' [patent_app_type] => utility [patent_app_number] => 15/456315 [patent_app_country] => US [patent_app_date] => 2017-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10693 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15456315 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/456315
Apparatus and method for determining log likelihood values of nodes in communication system supporting low density parity check code Mar 9, 2017 Issued
Array ( [id] => 11606590 [patent_doc_number] => 20170123893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'FLASH MEMORY CODEWORD ARCHITECTURES' [patent_app_type] => utility [patent_app_number] => 15/408476 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8284 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408476 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408476
Validation bits and offsets to represent logical pages split between data containers Jan 17, 2017 Issued
Array ( [id] => 11606592 [patent_doc_number] => 20170123895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'FLASH MEMORY CODEWORD ARCHITECTURES' [patent_app_type] => utility [patent_app_number] => 15/408508 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8282 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408508 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408508
Validation bits and offsets to represent logical pages split between data containers Jan 17, 2017 Issued
Array ( [id] => 13307717 [patent_doc_number] => 20180205395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => ADAPTIVE DOWNLINK CONTROL CHANNEL STRUCTURE FOR 5G OR OTHER NEXT GENERATION NETWORKS [patent_app_type] => utility [patent_app_number] => 15/408202 [patent_app_country] => US [patent_app_date] => 2017-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9997 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408202 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408202
Adaptive downlink control channel structure for 5G or other next generation networks Jan 16, 2017 Issued
Array ( [id] => 11623863 [patent_doc_number] => 20170134053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'FIXED POINT CONVERSION OF LLR VALUES BASED ON CORRELATION' [patent_app_type] => utility [patent_app_number] => 15/404619 [patent_app_country] => US [patent_app_date] => 2017-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5268 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15404619 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/404619
Fixed point conversion of LLR values based on correlation Jan 11, 2017 Issued
Array ( [id] => 11989294 [patent_doc_number] => 20170293449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'NONVOLATILE MEMORY DEVICE FOR PERFORMING A RANDOMIZED OPERATION' [patent_app_type] => utility [patent_app_number] => 15/401294 [patent_app_country] => US [patent_app_date] => 2017-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10013 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15401294 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/401294
Nonvolatile memory device for performing at least one of randomization operation and error correction operation Jan 8, 2017 Issued
Array ( [id] => 12213922 [patent_doc_number] => 09910731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'Resiliency to memory failures in computer systems' [patent_app_type] => utility [patent_app_number] => 15/357448 [patent_app_country] => US [patent_app_date] => 2016-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9327 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15357448 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/357448
Resiliency to memory failures in computer systems Nov 20, 2016 Issued
Array ( [id] => 12754240 [patent_doc_number] => 20180143247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => SCANNABLE DATA SYNCHRONIZER [patent_app_type] => utility [patent_app_number] => 15/356214 [patent_app_country] => US [patent_app_date] => 2016-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15356214 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/356214
Scannable data synchronizer Nov 17, 2016 Issued
Array ( [id] => 15016897 [patent_doc_number] => 10454619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Advanced retry mechanism for transmitting large datasets [patent_app_type] => utility [patent_app_number] => 15/346352 [patent_app_country] => US [patent_app_date] => 2016-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15346352 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/346352
Advanced retry mechanism for transmitting large datasets Nov 7, 2016 Issued
Array ( [id] => 13974175 [patent_doc_number] => 10216443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Proactively deselect storage units for access during major geographic events [patent_app_type] => utility [patent_app_number] => 15/340017 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6077 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340017 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340017
Proactively deselect storage units for access during major geographic events Oct 31, 2016 Issued
Array ( [id] => 14432685 [patent_doc_number] => 10321164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => System and method for improving graphics and other signal results through signal transformation and application of dithering [patent_app_type] => utility [patent_app_number] => 15/275011 [patent_app_country] => US [patent_app_date] => 2016-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 8441 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15275011 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/275011
System and method for improving graphics and other signal results through signal transformation and application of dithering Sep 22, 2016 Issued
Array ( [id] => 14009481 [patent_doc_number] => 10223199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Non-volatile memory configured to return error reduced read data [patent_app_type] => utility [patent_app_number] => 15/274037 [patent_app_country] => US [patent_app_date] => 2016-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 13968 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15274037 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/274037
Non-volatile memory configured to return error reduced read data Sep 22, 2016 Issued
Array ( [id] => 13710497 [patent_doc_number] => 20170366203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => HOLOGRAPHIC DATA STORAGE SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 15/272446 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15272446 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/272446
HOLOGRAPHIC DATA STORAGE SYSTEM AND METHOD Sep 21, 2016 Abandoned
Array ( [id] => 11531048 [patent_doc_number] => 20170091026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'Storing Address of Spare in Failed Memory Location' [patent_app_type] => utility [patent_app_number] => 15/273208 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6949 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273208 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/273208
Storing address of spare in failed memory location Sep 21, 2016 Issued
Array ( [id] => 12262558 [patent_doc_number] => 20180081754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'METHOD OF OPERATING MEMORY DEVICE, MEMORY DEVICE USING THE SAME AND MEMORY SYSTEM INCLUDING THE DEVICE' [patent_app_type] => utility [patent_app_number] => 15/270292 [patent_app_country] => US [patent_app_date] => 2016-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5730 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270292 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/270292
Method of operating memory device using a compressed party difference, memory device using the same and memory system including the device Sep 19, 2016 Issued
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