David Morgan Fenstermacher

Array ( [id] => 18757668 [patent_doc_number] => 20230361131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/352273 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8041 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18757540 [patent_doc_number] => 20230361003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING [patent_app_type] => utility [patent_app_number] => 18/216040 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18216040 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18759675 [patent_doc_number] => 20230363164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => MICROELECTRONIC DEVICES AND RELATED MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/343383 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12823 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18343383 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18743439 [patent_doc_number] => 20230352427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => SEMICONDUCTOR DIE INCLUDING GUARD RING STRUCTURE AND THREE-DIMENSIONAL DEVICE STRUCTURE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/338596 [patent_app_country] => US [patent_app_date] => 2023-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18338596 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19262580 [patent_doc_number] => 12022665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Semiconductor device and method for forming the same [patent_app_type] => utility [patent_app_number] => 18/335816 [patent_app_country] => US [patent_app_date] => 2023-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 46 [patent_no_of_words] => 11264 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18335816 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18696412 [patent_doc_number] => 20230326851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => BACKSIDE CONNECTION STRUCTURES FOR NANOSTRUCTURES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/335175 [patent_app_country] => US [patent_app_date] => 2023-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16888 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18335175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18680003 [patent_doc_number] => 20230317661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => Multi-Bump Connection to Interconnect Structure and Manufacturing Method Thereof [patent_app_type] => utility [patent_app_number] => 18/327252 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7541 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327252 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18745650 [patent_doc_number] => 20230354644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => DISPLAY DEVICE, METHOD OF MANUFACTURING DISPLAY DEVICE, AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 18/196744 [patent_app_country] => US [patent_app_date] => 2023-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20432 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18196744 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18600400 [patent_doc_number] => 20230275202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => LIGHT EMITTING DIODES WITH ENHANCED THERMAL SINKING AND ASSOCIATED METHODS OF OPERATION [patent_app_type] => utility [patent_app_number] => 18/311834 [patent_app_country] => US [patent_app_date] => 2023-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18311834 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18570565 [patent_doc_number] => 20230260902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => SEMICONDUCTOR DEVICE WITH SOURCE RESISTOR [patent_app_type] => utility [patent_app_number] => 18/304261 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8350 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18304261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18600175 [patent_doc_number] => 20230274976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => Processes for Reducing Leakage and Improving Adhesion [patent_app_type] => utility [patent_app_number] => 18/302545 [patent_app_country] => US [patent_app_date] => 2023-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7687 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18302545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18555339 [patent_doc_number] => 20230253356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => CHIP STRUCTURE WITH CONDUCTIVE PILLAR AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/302228 [patent_app_country] => US [patent_app_date] => 2023-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18302228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18555278 [patent_doc_number] => 20230253295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING [patent_app_type] => utility [patent_app_number] => 18/132801 [patent_app_country] => US [patent_app_date] => 2023-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5658 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18132801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18514680 [patent_doc_number] => 20230230941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/126996 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18126996 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18502348 [patent_doc_number] => 20230225227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => NON-VOLATILE MEMORY STRUCTURE WITH POSITIONED DOPING [patent_app_type] => utility [patent_app_number] => 18/114419 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18114419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18456268 [patent_doc_number] => 20230197550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => PASSIVATION LAYER FOR A SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/173837 [patent_app_country] => US [patent_app_date] => 2023-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18173837 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18440268 [patent_doc_number] => 20230187563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/164642 [patent_app_country] => US [patent_app_date] => 2023-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18164642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18362916 [patent_doc_number] => 20230144507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => RESISTOR WITH DOPED REGIONS AND SEMICONDUCTOR DEVICES HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 18/148810 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18148810 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19199142 [patent_doc_number] => 11996391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 18/057885 [patent_app_country] => US [patent_app_date] => 2022-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18057885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18999212 [patent_doc_number] => 11916068 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Type III-V semiconductor substrate with monolithically integrated capacitor [patent_app_type] => utility [patent_app_number] => 17/977875 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5288 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17977875 [rel_patent_id] =>[rel_patent_doc_number] =>)