Search

David Morgan Fenstermacher

Examiner (ID: 12073, Phone: (571)272-7102 , Office: P/3658 )

Most Active Art Unit
3682
Art Unit(s)
3681, 2714, 3656, 1764, 3502, 3658, 3622, 3682
Total Applications
2283
Issued Applications
1955
Pending Applications
70
Abandoned Applications
264

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7510736 [patent_doc_number] => 08037447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Identifying semiconductor system specification violations' [patent_app_type] => utility [patent_app_number] => 12/907814 [patent_app_country] => US [patent_app_date] => 2010-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3722 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/037/08037447.pdf [firstpage_image] =>[orig_patent_app_number] => 12907814 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/907814
Identifying semiconductor system specification violations Oct 18, 2010 Issued
Array ( [id] => 6141099 [patent_doc_number] => 20110010684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-13 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DESIGNING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/885744 [patent_app_country] => US [patent_app_date] => 2010-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6213 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20110010684.pdf [firstpage_image] =>[orig_patent_app_number] => 12885744 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/885744
SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DESIGNING THE SAME Sep 19, 2010 Abandoned
Array ( [id] => 6167134 [patent_doc_number] => 20110161898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'Synthesizing Checkers from Nondeterministic Finite Automaton' [patent_app_type] => utility [patent_app_number] => 12/873234 [patent_app_country] => US [patent_app_date] => 2010-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3896 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20110161898.pdf [firstpage_image] =>[orig_patent_app_number] => 12873234 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/873234
Synthesizing Checkers from Nondeterministic Finite Automaton Aug 30, 2010 Abandoned
Array ( [id] => 5960936 [patent_doc_number] => 20110185323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'Stacked Integracted Circuit Verification' [patent_app_type] => utility [patent_app_number] => 12/861824 [patent_app_country] => US [patent_app_date] => 2010-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8824 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20110185323.pdf [firstpage_image] =>[orig_patent_app_number] => 12861824 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/861824
Stacked Integracted Circuit Verification Aug 22, 2010 Abandoned
Array ( [id] => 5996701 [patent_doc_number] => 20110016445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'Layout design system and layout design method' [patent_app_type] => utility [patent_app_number] => 12/801864 [patent_app_country] => US [patent_app_date] => 2010-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 11535 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20110016445.pdf [firstpage_image] =>[orig_patent_app_number] => 12801864 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/801864
Layout design system and layout design method Jun 28, 2010 Abandoned
Array ( [id] => 6009000 [patent_doc_number] => 20110061032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-10 [patent_title] => 'HIGH-LEVEL SYNTHESIS APPARATUS, HIGH-LEVEL SYNTHESIS METHOD, AND COMPUTER READABLE MEDIUM COMPRISING HIGH-LEVEL SYNTHESIS PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/730104 [patent_app_country] => US [patent_app_date] => 2010-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6848 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20110061032.pdf [firstpage_image] =>[orig_patent_app_number] => 12730104 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/730104
HIGH-LEVEL SYNTHESIS APPARATUS, HIGH-LEVEL SYNTHESIS METHOD, AND COMPUTER READABLE MEDIUM COMPRISING HIGH-LEVEL SYNTHESIS PROGRAM Mar 22, 2010 Abandoned
Array ( [id] => 6088459 [patent_doc_number] => 20110145775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'CELL LIBRARY, LAYOUT METHOD, AND LAYOUT APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/723554 [patent_app_country] => US [patent_app_date] => 2010-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7622 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20110145775.pdf [firstpage_image] =>[orig_patent_app_number] => 12723554 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/723554
CELL LIBRARY, LAYOUT METHOD, AND LAYOUT APPARATUS Mar 11, 2010 Abandoned
Array ( [id] => 6451101 [patent_doc_number] => 20100153892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'METHODS TO OBTAIN A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIRCUIT LAYOUT OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 12/712880 [patent_app_country] => US [patent_app_date] => 2010-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8587 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20100153892.pdf [firstpage_image] =>[orig_patent_app_number] => 12712880 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/712880
Methods to obtain a feasible integer solution in a hierarchical circuit layout optimization Feb 24, 2010 Issued
Array ( [id] => 6492906 [patent_doc_number] => 20100042958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 12/582453 [patent_app_country] => US [patent_app_date] => 2009-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5942 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20100042958.pdf [firstpage_image] =>[orig_patent_app_number] => 12582453 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/582453
ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE Oct 19, 2009 Abandoned
Array ( [id] => 6612572 [patent_doc_number] => 20100131915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'Method, device, and program for predicting a manufacturing defect part of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/585444 [patent_app_country] => US [patent_app_date] => 2009-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8142 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20100131915.pdf [firstpage_image] =>[orig_patent_app_number] => 12585444 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/585444
Method, device, and program for predicting a manufacturing defect part of a semiconductor device Sep 14, 2009 Abandoned
Array ( [id] => 4479748 [patent_doc_number] => 07945872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-17 [patent_title] => 'Verifying an IC layout in individual regions and combining results' [patent_app_type] => utility [patent_app_number] => 12/559478 [patent_app_country] => US [patent_app_date] => 2009-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 46 [patent_no_of_words] => 11296 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/945/07945872.pdf [firstpage_image] =>[orig_patent_app_number] => 12559478 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/559478
Verifying an IC layout in individual regions and combining results Sep 13, 2009 Issued
Array ( [id] => 8343230 [patent_doc_number] => 08245168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Method and apparatus for generating memory models and timing database' [patent_app_type] => utility [patent_app_number] => 12/508320 [patent_app_country] => US [patent_app_date] => 2009-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7411 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12508320 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/508320
Method and apparatus for generating memory models and timing database Jul 22, 2009 Issued
Array ( [id] => 5326090 [patent_doc_number] => 20090064080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/261027 [patent_app_country] => US [patent_app_date] => 2008-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5062 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20090064080.pdf [firstpage_image] =>[orig_patent_app_number] => 12261027 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/261027
BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS Oct 28, 2008 Abandoned
Array ( [id] => 8285830 [patent_doc_number] => 08219947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Method and apparatus for merging EDA coverage logs of coverage data' [patent_app_type] => utility [patent_app_number] => 12/210876 [patent_app_country] => US [patent_app_date] => 2008-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8882 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12210876 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/210876
Method and apparatus for merging EDA coverage logs of coverage data Sep 14, 2008 Issued
Array ( [id] => 5298373 [patent_doc_number] => 20090013299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/207498 [patent_app_country] => US [patent_app_date] => 2008-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5064 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20090013299.pdf [firstpage_image] =>[orig_patent_app_number] => 12207498 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/207498
BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS Sep 9, 2008 Abandoned
Array ( [id] => 4951254 [patent_doc_number] => 20080307380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'Operational Cycle Assignment in a Configurable IC' [patent_app_type] => utility [patent_app_number] => 12/193713 [patent_app_country] => US [patent_app_date] => 2008-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 15302 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20080307380.pdf [firstpage_image] =>[orig_patent_app_number] => 12193713 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/193713
Operational cycle assignment in a configurable IC Aug 17, 2008 Issued
Array ( [id] => 5363068 [patent_doc_number] => 20090037862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Operational Cycle Assignment in a Configurable IC' [patent_app_type] => utility [patent_app_number] => 12/193707 [patent_app_country] => US [patent_app_date] => 2008-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 15302 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037862.pdf [firstpage_image] =>[orig_patent_app_number] => 12193707 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/193707
Operational cycle assignment in a configurable IC Aug 17, 2008 Issued
Array ( [id] => 4951252 [patent_doc_number] => 20080307378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'Operational Cycle Assignment in a Configurable IC' [patent_app_type] => utility [patent_app_number] => 12/193712 [patent_app_country] => US [patent_app_date] => 2008-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 15302 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20080307378.pdf [firstpage_image] =>[orig_patent_app_number] => 12193712 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/193712
Operational cycle assignment in a configurable IC Aug 17, 2008 Issued
Array ( [id] => 122684 [patent_doc_number] => 07704837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Cell based integrated circuit and unit cell architecture therefor' [patent_app_type] => utility [patent_app_number] => 12/187474 [patent_app_country] => US [patent_app_date] => 2008-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4602 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/704/07704837.pdf [firstpage_image] =>[orig_patent_app_number] => 12187474 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/187474
Cell based integrated circuit and unit cell architecture therefor Aug 6, 2008 Issued
Array ( [id] => 8031269 [patent_doc_number] => 08144726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'Structure for out of band signaling enhancement for high speed serial driver' [patent_app_type] => utility [patent_app_number] => 12/154796 [patent_app_country] => US [patent_app_date] => 2008-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5369 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/144/08144726.pdf [firstpage_image] =>[orig_patent_app_number] => 12154796 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/154796
Structure for out of band signaling enhancement for high speed serial driver May 26, 2008 Issued
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