Search

David Nhu

Examiner (ID: 12263, Phone: (571)272-1792 , Office: P/2817 )

Most Active Art Unit
2818
Art Unit(s)
2895, 2818, 2817
Total Applications
2355
Issued Applications
2255
Pending Applications
12
Abandoned Applications
91

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6153787 [patent_doc_number] => 20110156254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'MODIFIED CHIP ATTACH PROCESS' [patent_app_type] => utility [patent_app_number] => 13/042239 [patent_app_country] => US [patent_app_date] => 2011-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4860 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20110156254.pdf [firstpage_image] =>[orig_patent_app_number] => 13042239 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/042239
Modified chip attach process Mar 6, 2011 Issued
Array ( [id] => 8549201 [patent_doc_number] => 08324081 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-04 [patent_title] => 'Wafer level surface passivation of stackable integrated circuit chips' [patent_app_type] => utility [patent_app_number] => 13/041192 [patent_app_country] => US [patent_app_date] => 2011-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 41 [patent_no_of_words] => 11886 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13041192 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/041192
Wafer level surface passivation of stackable integrated circuit chips Mar 3, 2011 Issued
Array ( [id] => 9127036 [patent_doc_number] => 08574985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-05 [patent_title] => 'Methods for depositing high-K dielectrics' [patent_app_type] => utility [patent_app_number] => 13/039819 [patent_app_country] => US [patent_app_date] => 2011-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4386 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13039819 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/039819
Methods for depositing high-K dielectrics Mar 2, 2011 Issued
Array ( [id] => 8469680 [patent_doc_number] => 08298859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Semiconductor connection component' [patent_app_type] => utility [patent_app_number] => 13/035273 [patent_app_country] => US [patent_app_date] => 2011-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 7675 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13035273 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/035273
Semiconductor connection component Feb 24, 2011 Issued
Array ( [id] => 8352000 [patent_doc_number] => 08247329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-21 [patent_title] => 'Nanotube semiconductor devices' [patent_app_type] => utility [patent_app_number] => 13/024256 [patent_app_country] => US [patent_app_date] => 2011-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 60 [patent_no_of_words] => 16710 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13024256 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/024256
Nanotube semiconductor devices Feb 8, 2011 Issued
Array ( [id] => 6075384 [patent_doc_number] => 20110140274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'FORMING THICK METAL INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/023191 [patent_app_country] => US [patent_app_date] => 2011-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4504 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20110140274.pdf [firstpage_image] =>[orig_patent_app_number] => 13023191 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/023191
Forming thick metal interconnect structures for integrated circuits Feb 7, 2011 Issued
Array ( [id] => 6175280 [patent_doc_number] => 20110120377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'REMOTE PLASMA PROCESSING OF INTERFACE SURFACES' [patent_app_type] => utility [patent_app_number] => 13/019854 [patent_app_country] => US [patent_app_date] => 2011-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20110120377.pdf [firstpage_image] =>[orig_patent_app_number] => 13019854 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/019854
Remote plasma processing of interface surfaces Feb 1, 2011 Issued
Array ( [id] => 8625068 [patent_doc_number] => 08357562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-22 [patent_title] => 'Method to improve the reliability of the breakdown voltage in high voltage devices' [patent_app_type] => utility [patent_app_number] => 13/015666 [patent_app_country] => US [patent_app_date] => 2011-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2872 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13015666 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/015666
Method to improve the reliability of the breakdown voltage in high voltage devices Jan 27, 2011 Issued
Array ( [id] => 8363628 [patent_doc_number] => 08252693 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-28 [patent_title] => 'Self-alignment for semiconductor patterns' [patent_app_type] => utility [patent_app_number] => 13/015514 [patent_app_country] => US [patent_app_date] => 2011-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7074 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13015514 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/015514
Self-alignment for semiconductor patterns Jan 26, 2011 Issued
Array ( [id] => 8458603 [patent_doc_number] => 08294274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Semiconductor contact barrier' [patent_app_type] => utility [patent_app_number] => 13/015328 [patent_app_country] => US [patent_app_date] => 2011-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4070 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13015328 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/015328
Semiconductor contact barrier Jan 26, 2011 Issued
Array ( [id] => 8210167 [patent_doc_number] => 20120129278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'DRY ETCHING METHOD' [patent_app_type] => utility [patent_app_number] => 13/387670 [patent_app_country] => US [patent_app_date] => 2011-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10800 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20120129278.pdf [firstpage_image] =>[orig_patent_app_number] => 13387670 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/387670
Dry etching method Jan 24, 2011 Issued
Array ( [id] => 9020375 [patent_doc_number] => 08530360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Method for low stress flip-chip assembly of fine-pitch semiconductor devices' [patent_app_type] => utility [patent_app_number] => 13/013438 [patent_app_country] => US [patent_app_date] => 2011-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5339 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13013438 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/013438
Method for low stress flip-chip assembly of fine-pitch semiconductor devices Jan 24, 2011 Issued
Array ( [id] => 6051430 [patent_doc_number] => 20110108542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND THERMAL ANNEALING APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/009904 [patent_app_country] => US [patent_app_date] => 2011-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11105 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20110108542.pdf [firstpage_image] =>[orig_patent_app_number] => 13009904 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/009904
Method of manufacturing semiconductor device and thermal annealing apparatus Jan 19, 2011 Issued
Array ( [id] => 6177644 [patent_doc_number] => 20110121378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'ZrXHfYSn1-X-YO2 FILMS AS HIGH K GATE DIELECTRICS' [patent_app_type] => utility [patent_app_number] => 13/008726 [patent_app_country] => US [patent_app_date] => 2011-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10513 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20110121378.pdf [firstpage_image] =>[orig_patent_app_number] => 13008726 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/008726
ZrXHfYSn1-X-YO2 films as high K gate dielectrics Jan 17, 2011 Issued
Array ( [id] => 5940831 [patent_doc_number] => 20110101451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'SEMICONDUCTOR COMPONENT STRUCTURE WITH VERTICAL DIELECTRIC LAYERS' [patent_app_type] => utility [patent_app_number] => 12/984934 [patent_app_country] => US [patent_app_date] => 2011-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13274 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20110101451.pdf [firstpage_image] =>[orig_patent_app_number] => 12984934 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/984934
Semiconductor component structure with vertical dielectric layers Jan 4, 2011 Issued
Array ( [id] => 9817649 [patent_doc_number] => 08927433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-06 [patent_title] => 'Conductive via hole and method for forming conductive via hole' [patent_app_type] => utility [patent_app_number] => 12/969469 [patent_app_country] => US [patent_app_date] => 2010-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3826 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12969469 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/969469
Conductive via hole and method for forming conductive via hole Dec 14, 2010 Issued
Array ( [id] => 9889474 [patent_doc_number] => 08975734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-10 [patent_title] => 'Semiconductor package without chip carrier and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 12/967839 [patent_app_country] => US [patent_app_date] => 2010-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 5145 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12967839 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/967839
Semiconductor package without chip carrier and fabrication method thereof Dec 13, 2010 Issued
Array ( [id] => 6114502 [patent_doc_number] => 20110073981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/965367 [patent_app_country] => US [patent_app_date] => 2010-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9472 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20110073981.pdf [firstpage_image] =>[orig_patent_app_number] => 12965367 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/965367
Semiconductor device and method for manufacturing the same Dec 9, 2010 Issued
Array ( [id] => 6026863 [patent_doc_number] => 20110079812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-07 [patent_title] => 'LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/964685 [patent_app_country] => US [patent_app_date] => 2010-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3669 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20110079812.pdf [firstpage_image] =>[orig_patent_app_number] => 12964685 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/964685
Light emitting device and method for manufacturing the same Dec 8, 2010 Issued
Array ( [id] => 6199797 [patent_doc_number] => 20110062583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'STACKED DIE PACKAGE FOR PERIPHERAL AND CENTER DEVICE PAD LAYOUT DEVICE' [patent_app_type] => utility [patent_app_number] => 12/950654 [patent_app_country] => US [patent_app_date] => 2010-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7484 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20110062583.pdf [firstpage_image] =>[orig_patent_app_number] => 12950654 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/950654
Stacked die package for peripheral and center device pad layout device Nov 18, 2010 Issued
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