
David Nhu
Examiner (ID: 12263, Phone: (571)272-1792 , Office: P/2817 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2895, 2818, 2817 |
| Total Applications | 2355 |
| Issued Applications | 2255 |
| Pending Applications | 12 |
| Abandoned Applications | 91 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
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[id] => 6153787
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Array
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Array
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