Search

David Nhu

Examiner (ID: 12263, Phone: (571)272-1792 , Office: P/2817 )

Most Active Art Unit
2818
Art Unit(s)
2895, 2818, 2817
Total Applications
2355
Issued Applications
2255
Pending Applications
12
Abandoned Applications
91

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5575520 [patent_doc_number] => 20090142882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'Phase Change Memories With Improved Programming Characteristics' [patent_app_type] => utility [patent_app_number] => 12/364698 [patent_app_country] => US [patent_app_date] => 2009-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2596 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20090142882.pdf [firstpage_image] =>[orig_patent_app_number] => 12364698 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/364698
Phase change memories with improved programming characteristics Feb 2, 2009 Issued
Array ( [id] => 5524349 [patent_doc_number] => 20090194425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'Electrochemical Fabrication Methods Including Use of Surface Treatments to Reduce Overplating and/or Planarization During Formation of Multi-layer Three-Dimensional Structures' [patent_app_type] => utility [patent_app_number] => 12/362175 [patent_app_country] => US [patent_app_date] => 2009-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 20403 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20090194425.pdf [firstpage_image] =>[orig_patent_app_number] => 12362175 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/362175
Electrochemical Fabrication Methods Including Use of Surface Treatments to Reduce Overplating and/or Planarization During Formation of Multi-layer Three-Dimensional Structures Jan 28, 2009 Abandoned
Array ( [id] => 4557858 [patent_doc_number] => 07838379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'Non-volatile memory device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/362277 [patent_app_country] => US [patent_app_date] => 2009-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 49 [patent_no_of_words] => 10381 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/838/07838379.pdf [firstpage_image] =>[orig_patent_app_number] => 12362277 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/362277
Non-volatile memory device and method of manufacturing the same Jan 28, 2009 Issued
Array ( [id] => 4435432 [patent_doc_number] => 07898083 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Method for low stress flip-chip assembly of fine-pitch semiconductor devices' [patent_app_type] => utility [patent_app_number] => 12/361768 [patent_app_country] => US [patent_app_date] => 2009-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5297 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/898/07898083.pdf [firstpage_image] =>[orig_patent_app_number] => 12361768 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/361768
Method for low stress flip-chip assembly of fine-pitch semiconductor devices Jan 28, 2009 Issued
Array ( [id] => 4487421 [patent_doc_number] => 07902613 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-08 [patent_title] => 'Self-alignment for semiconductor patterns' [patent_app_type] => utility [patent_app_number] => 12/361407 [patent_app_country] => US [patent_app_date] => 2009-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7046 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/902/07902613.pdf [firstpage_image] =>[orig_patent_app_number] => 12361407 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/361407
Self-alignment for semiconductor patterns Jan 27, 2009 Issued
Array ( [id] => 7709930 [patent_doc_number] => 08092161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-10 [patent_title] => 'Thermal shield at casing joint' [patent_app_type] => utility [patent_app_number] => 12/355025 [patent_app_country] => US [patent_app_date] => 2009-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6453 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/092/08092161.pdf [firstpage_image] =>[orig_patent_app_number] => 12355025 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/355025
Thermal shield at casing joint Jan 15, 2009 Issued
Array ( [id] => 6428948 [patent_doc_number] => 20100143150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'FAN MOUNTING ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 12/354782 [patent_app_country] => US [patent_app_date] => 2009-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 883 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20100143150.pdf [firstpage_image] =>[orig_patent_app_number] => 12354782 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/354782
Fan mounting assembly Jan 15, 2009 Issued
Array ( [id] => 5498521 [patent_doc_number] => 20090159209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'PLASMA ETCHING METHOD AND PLASMA ETCHING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/354994 [patent_app_country] => US [patent_app_date] => 2009-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5174 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20090159209.pdf [firstpage_image] =>[orig_patent_app_number] => 12354994 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/354994
PLASMA ETCHING METHOD AND PLASMA ETCHING APPARATUS Jan 15, 2009 Abandoned
Array ( [id] => 6342493 [patent_doc_number] => 20100084718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'ADVANCED METAL GATE METHOD AND DEVICE' [patent_app_type] => utility [patent_app_number] => 12/354558 [patent_app_country] => US [patent_app_date] => 2009-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4797 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20100084718.pdf [firstpage_image] =>[orig_patent_app_number] => 12354558 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/354558
Advanced metal gate method and device Jan 14, 2009 Issued
Array ( [id] => 5527306 [patent_doc_number] => 20090197383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'METHOD OF FABRICATING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/353398 [patent_app_country] => US [patent_app_date] => 2009-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3510 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20090197383.pdf [firstpage_image] =>[orig_patent_app_number] => 12353398 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/353398
Method of fabricating a semiconductor device Jan 13, 2009 Issued
Array ( [id] => 23545 [patent_doc_number] => 07795074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'WLCSP target and method for forming the same' [patent_app_type] => utility [patent_app_number] => 12/352858 [patent_app_country] => US [patent_app_date] => 2009-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 3469 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/795/07795074.pdf [firstpage_image] =>[orig_patent_app_number] => 12352858 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/352858
WLCSP target and method for forming the same Jan 12, 2009 Issued
Array ( [id] => 4432541 [patent_doc_number] => 07897414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Method of manufacturing semiconductor device and thermal annealing apparatus' [patent_app_type] => utility [patent_app_number] => 12/350238 [patent_app_country] => US [patent_app_date] => 2009-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 11111 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/897/07897414.pdf [firstpage_image] =>[orig_patent_app_number] => 12350238 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/350238
Method of manufacturing semiconductor device and thermal annealing apparatus Jan 7, 2009 Issued
Array ( [id] => 7771419 [patent_doc_number] => 08118544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Bearing and retention mechanisms' [patent_app_type] => utility [patent_app_number] => 12/350029 [patent_app_country] => US [patent_app_date] => 2009-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5294 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/118/08118544.pdf [firstpage_image] =>[orig_patent_app_number] => 12350029 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/350029
Bearing and retention mechanisms Jan 6, 2009 Issued
Array ( [id] => 6624747 [patent_doc_number] => 20100172746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'METHOD AND APPARATUS FOR COOLING A TRANSITION PIECE' [patent_app_type] => utility [patent_app_number] => 12/349221 [patent_app_country] => US [patent_app_date] => 2009-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2069 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20100172746.pdf [firstpage_image] =>[orig_patent_app_number] => 12349221 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/349221
Method and apparatus for cooling a transition piece Jan 5, 2009 Issued
Array ( [id] => 7522989 [patent_doc_number] => 08026145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-27 [patent_title] => 'Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering' [patent_app_type] => utility [patent_app_number] => 12/347336 [patent_app_country] => US [patent_app_date] => 2008-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 6879 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/026/08026145.pdf [firstpage_image] =>[orig_patent_app_number] => 12347336 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/347336
Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering Dec 30, 2008 Issued
Array ( [id] => 4009 [patent_doc_number] => 07816169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Colors only process to reduce package yield loss' [patent_app_type] => utility [patent_app_number] => 12/347468 [patent_app_country] => US [patent_app_date] => 2008-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5085 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/816/07816169.pdf [firstpage_image] =>[orig_patent_app_number] => 12347468 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/347468
Colors only process to reduce package yield loss Dec 30, 2008 Issued
Array ( [id] => 6255020 [patent_doc_number] => 20100029018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'METHOD FOR REPAIR OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/346708 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2495 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20100029018.pdf [firstpage_image] =>[orig_patent_app_number] => 12346708 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/346708
Method for repair of semiconductor device Dec 29, 2008 Issued
Array ( [id] => 23544 [patent_doc_number] => 07795073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Method for manufacturing stack package using through-electrodes' [patent_app_type] => utility [patent_app_number] => 12/345858 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3085 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/795/07795073.pdf [firstpage_image] =>[orig_patent_app_number] => 12345858 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345858
Method for manufacturing stack package using through-electrodes Dec 29, 2008 Issued
Array ( [id] => 13711 [patent_doc_number] => 07803715 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-28 [patent_title] => 'Lithographic patterning for sub-90nm with a multi-layered carbon-based hardmask' [patent_app_type] => utility [patent_app_number] => 12/345568 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5408 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/803/07803715.pdf [firstpage_image] =>[orig_patent_app_number] => 12345568 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345568
Lithographic patterning for sub-90nm with a multi-layered carbon-based hardmask Dec 28, 2008 Issued
Array ( [id] => 6419311 [patent_doc_number] => 20100167511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'METHODS FOR SIMULTANEOUSLY FORMING DOPED REGIONS HAVING DIFFERENT CONDUCTIVITY-DETERMINING TYPE ELEMENT PROFILES' [patent_app_type] => utility [patent_app_number] => 12/344748 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5849 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20100167511.pdf [firstpage_image] =>[orig_patent_app_number] => 12344748 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/344748
Methods for simultaneously forming doped regions having different conductivity-determining type element profiles Dec 28, 2008 Issued
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