Search

David Nhu

Examiner (ID: 12263, Phone: (571)272-1792 , Office: P/2817 )

Most Active Art Unit
2818
Art Unit(s)
2895, 2818, 2817
Total Applications
2355
Issued Applications
2255
Pending Applications
12
Abandoned Applications
91

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 195872 [patent_doc_number] => 07635648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-22 [patent_title] => 'Methods for fabricating dual material gate in a semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/100557 [patent_app_country] => US [patent_app_date] => 2008-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4225 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/635/07635648.pdf [firstpage_image] =>[orig_patent_app_number] => 12100557 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/100557
Methods for fabricating dual material gate in a semiconductor device Apr 9, 2008 Issued
Array ( [id] => 5458312 [patent_doc_number] => 20090258464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-15 [patent_title] => 'METHODS FOR MANUFACTURING A HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR USING A HYBRID ORIENTATION TECHNOLOGY WAFER' [patent_app_type] => utility [patent_app_number] => 12/099904 [patent_app_country] => US [patent_app_date] => 2008-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4914 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20090258464.pdf [firstpage_image] =>[orig_patent_app_number] => 12099904 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/099904
METHODS FOR MANUFACTURING A HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR USING A HYBRID ORIENTATION TECHNOLOGY WAFER Apr 8, 2008 Abandoned
Array ( [id] => 4663694 [patent_doc_number] => 20080254601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'METHODS FOR OPTIMIZING THIN FILM FORMATION WITH REACTIVE GASES' [patent_app_type] => utility [patent_app_number] => 12/060528 [patent_app_country] => US [patent_app_date] => 2008-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12636 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20080254601.pdf [firstpage_image] =>[orig_patent_app_number] => 12060528 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/060528
Methods for optimizing thin film formation with reactive gases Mar 31, 2008 Issued
Array ( [id] => 205337 [patent_doc_number] => 07629668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-08 [patent_title] => 'Composite semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/078323 [patent_app_country] => US [patent_app_date] => 2008-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4384 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/629/07629668.pdf [firstpage_image] =>[orig_patent_app_number] => 12078323 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/078323
Composite semiconductor device Mar 27, 2008 Issued
Array ( [id] => 228788 [patent_doc_number] => 07601601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/078214 [patent_app_country] => US [patent_app_date] => 2008-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 60 [patent_no_of_words] => 20488 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/601/07601601.pdf [firstpage_image] =>[orig_patent_app_number] => 12078214 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/078214
Method for manufacturing semiconductor device Mar 27, 2008 Issued
Array ( [id] => 5422520 [patent_doc_number] => 20090148975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'Method of manufacturing nitride semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/078063 [patent_app_country] => US [patent_app_date] => 2008-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7545 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20090148975.pdf [firstpage_image] =>[orig_patent_app_number] => 12078063 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/078063
Method of manufacturing nitride semiconductor device Mar 25, 2008 Abandoned
Array ( [id] => 4663690 [patent_doc_number] => 20080254597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'Method for manufacturing SOI substrate' [patent_app_type] => utility [patent_app_number] => 12/076923 [patent_app_country] => US [patent_app_date] => 2008-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3566 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20080254597.pdf [firstpage_image] =>[orig_patent_app_number] => 12076923 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/076923
Method for manufacturing SOI substrate Mar 24, 2008 Issued
Array ( [id] => 5404003 [patent_doc_number] => 20090239317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'Method and jig structure for positioning bare dice' [patent_app_type] => utility [patent_app_number] => 12/076674 [patent_app_country] => US [patent_app_date] => 2008-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2256 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20090239317.pdf [firstpage_image] =>[orig_patent_app_number] => 12076674 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/076674
Method and jig structure for positioning bare dice Mar 20, 2008 Issued
Array ( [id] => 121498 [patent_doc_number] => 07709337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-04 [patent_title] => 'Method for manufacturing SOI substrate and semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/076763 [patent_app_country] => US [patent_app_date] => 2008-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 54 [patent_no_of_words] => 20177 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/709/07709337.pdf [firstpage_image] =>[orig_patent_app_number] => 12076763 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/076763
Method for manufacturing SOI substrate and semiconductor device Mar 20, 2008 Issued
Array ( [id] => 288974 [patent_doc_number] => 07547587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-16 [patent_title] => 'Method for manufacturing semiconductor light emitting device' [patent_app_type] => utility [patent_app_number] => 12/052777 [patent_app_country] => US [patent_app_date] => 2008-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 29 [patent_no_of_words] => 2875 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/547/07547587.pdf [firstpage_image] =>[orig_patent_app_number] => 12052777 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/052777
Method for manufacturing semiconductor light emitting device Mar 20, 2008 Issued
Array ( [id] => 4765139 [patent_doc_number] => 20080176350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than other imager device transistors' [patent_app_type] => utility [patent_app_number] => 12/076631 [patent_app_country] => US [patent_app_date] => 2008-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6801 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20080176350.pdf [firstpage_image] =>[orig_patent_app_number] => 12076631 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/076631
Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than other imager device transistors Mar 19, 2008 Issued
Array ( [id] => 5531978 [patent_doc_number] => 20090231766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'ELETROSTATIC DISCHARGE (ESD) DEVICE AND METHOD OF FABRICATING' [patent_app_type] => utility [patent_app_number] => 12/048461 [patent_app_country] => US [patent_app_date] => 2008-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3187 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20090231766.pdf [firstpage_image] =>[orig_patent_app_number] => 12048461 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/048461
Electrostatic discharge (ESD) device and method of fabricating Mar 13, 2008 Issued
Array ( [id] => 4927520 [patent_doc_number] => 20080166883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'HEMI-SPHERICAL STRUCTURE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/048006 [patent_app_country] => US [patent_app_date] => 2008-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3197 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20080166883.pdf [firstpage_image] =>[orig_patent_app_number] => 12048006 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/048006
Hemi-spherical structure and method for fabricating the same Mar 12, 2008 Issued
Array ( [id] => 4879850 [patent_doc_number] => 20080153233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'FLASH MEMORY WITH RECESSED FLOATING GATE' [patent_app_type] => utility [patent_app_number] => 12/045569 [patent_app_country] => US [patent_app_date] => 2008-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4524 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20080153233.pdf [firstpage_image] =>[orig_patent_app_number] => 12045569 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/045569
Flash memory with recessed floating gate Mar 9, 2008 Issued
Array ( [id] => 6587105 [patent_doc_number] => 20100047976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'METHOD FOR FORMING NITRIDE SEMICONDUCTOR LAMINATED STRUCTURE AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR ELEMENT' [patent_app_type] => utility [patent_app_number] => 12/531059 [patent_app_country] => US [patent_app_date] => 2008-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8539 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20100047976.pdf [firstpage_image] =>[orig_patent_app_number] => 12531059 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/531059
Method for forming a nitride semiconductor laminated structure and method for manufacturing a nitride semiconductor element Mar 6, 2008 Issued
Array ( [id] => 4570964 [patent_doc_number] => 07829378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Method of manufacturing electronic device, substrate and semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/044397 [patent_app_country] => US [patent_app_date] => 2008-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 5836 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/829/07829378.pdf [firstpage_image] =>[orig_patent_app_number] => 12044397 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/044397
Method of manufacturing electronic device, substrate and semiconductor device Mar 6, 2008 Issued
Array ( [id] => 4879810 [patent_doc_number] => 20080153193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'METHODS FOR FABRICATING SOLID STATE IMAGE SENSOR DEVICES HAVING NON-PLANAR TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 12/043526 [patent_app_country] => US [patent_app_date] => 2008-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 10530 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20080153193.pdf [firstpage_image] =>[orig_patent_app_number] => 12043526 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/043526
Methods for fabricating solid state image sensor devices having non-planar transistors Mar 5, 2008 Issued
Array ( [id] => 7597684 [patent_doc_number] => 07618893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-17 [patent_title] => 'Methods of forming a layer for barrier applications in an interconnect structure' [patent_app_type] => utility [patent_app_number] => 12/041804 [patent_app_country] => US [patent_app_date] => 2008-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 7083 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/618/07618893.pdf [firstpage_image] =>[orig_patent_app_number] => 12041804 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/041804
Methods of forming a layer for barrier applications in an interconnect structure Mar 3, 2008 Issued
Array ( [id] => 4879796 [patent_doc_number] => 20080153179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'Magnetic random access memory device and method of forming the same' [patent_app_type] => utility [patent_app_number] => 12/073098 [patent_app_country] => US [patent_app_date] => 2008-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6711 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20080153179.pdf [firstpage_image] =>[orig_patent_app_number] => 12073098 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/073098
Magnetic random access memory device and method of forming the same Feb 28, 2008 Issued
Array ( [id] => 5391785 [patent_doc_number] => 20090209098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'Multi-Step Cu Seed Layer Formation for Improving Sidewall Coverage' [patent_app_type] => utility [patent_app_number] => 12/031280 [patent_app_country] => US [patent_app_date] => 2008-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4318 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20090209098.pdf [firstpage_image] =>[orig_patent_app_number] => 12031280 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/031280
Multi-step Cu seed layer formation for improving sidewall coverage Feb 13, 2008 Issued
Menu