
David Nhu
Examiner (ID: 12263, Phone: (571)272-1792 , Office: P/2817 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2895, 2818, 2817 |
| Total Applications | 2355 |
| Issued Applications | 2255 |
| Pending Applications | 12 |
| Abandoned Applications | 91 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4845996
[patent_doc_number] => 20080182404
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-31
[patent_title] => 'NOVEL AIR GAP INTEGRATION SCHEME'
[patent_app_type] => utility
[patent_app_number] => 12/017930
[patent_app_country] => US
[patent_app_date] => 2008-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 9749
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0182/20080182404.pdf
[firstpage_image] =>[orig_patent_app_number] => 12017930
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/017930 | Air gap integration scheme | Jan 21, 2008 | Issued |
Array
(
[id] => 71649
[patent_doc_number] => 07754614
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-07-13
[patent_title] => 'Nonvolatile memory device and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 12/016100
[patent_app_country] => US
[patent_app_date] => 2008-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 2719
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/754/07754614.pdf
[firstpage_image] =>[orig_patent_app_number] => 12016100
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/016100 | Nonvolatile memory device and method for fabricating the same | Jan 16, 2008 | Issued |
Array
(
[id] => 5502311
[patent_doc_number] => 20090162999
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-25
[patent_title] => 'Method of Growing Nitride Semiconductor material'
[patent_app_type] => utility
[patent_app_number] => 12/014200
[patent_app_country] => US
[patent_app_date] => 2008-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2650
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0162/20090162999.pdf
[firstpage_image] =>[orig_patent_app_number] => 12014200
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/014200 | Method of growing nitride semiconductor material | Jan 14, 2008 | Issued |
Array
(
[id] => 5342831
[patent_doc_number] => 20090181481
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-16
[patent_title] => 'Method of Manufacturing an LED'
[patent_app_type] => utility
[patent_app_number] => 12/013687
[patent_app_country] => US
[patent_app_date] => 2008-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 1933
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0181/20090181481.pdf
[firstpage_image] =>[orig_patent_app_number] => 12013687
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/013687 | Method of manufacturing an LED | Jan 13, 2008 | Issued |
Array
(
[id] => 4810640
[patent_doc_number] => 20080191271
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-14
[patent_title] => 'SEMICONDUCTOR DEVICE HAVING FINS FET AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 11/972097
[patent_app_country] => US
[patent_app_date] => 2008-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 8479
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0191/20080191271.pdf
[firstpage_image] =>[orig_patent_app_number] => 11972097
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/972097 | Semiconductor device having fins FET and manufacturing method thereof | Jan 9, 2008 | Issued |
Array
(
[id] => 4487584
[patent_doc_number] => 07902642
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-08
[patent_title] => 'Resin composition for sealing light-emitting device and lamp'
[patent_app_type] => utility
[patent_app_number] => 12/374764
[patent_app_country] => US
[patent_app_date] => 2007-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 4797
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 33
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/902/07902642.pdf
[firstpage_image] =>[orig_patent_app_number] => 12374764
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/374764 | Resin composition for sealing light-emitting device and lamp | Dec 26, 2007 | Issued |
Array
(
[id] => 4879422
[patent_doc_number] => 20080152805
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-26
[patent_title] => 'Polysilicon Dummy Wafers and Process Used Therewith'
[patent_app_type] => utility
[patent_app_number] => 11/959354
[patent_app_country] => US
[patent_app_date] => 2007-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5946
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0152/20080152805.pdf
[firstpage_image] =>[orig_patent_app_number] => 11959354
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/959354 | Polysilicon dummy wafers and process used therewith | Dec 17, 2007 | Issued |
Array
(
[id] => 5542845
[patent_doc_number] => 20090152722
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-18
[patent_title] => 'Synergy Effect of Alloying Materials in Interconnect Structures'
[patent_app_type] => utility
[patent_app_number] => 11/959274
[patent_app_country] => US
[patent_app_date] => 2007-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3630
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0152/20090152722.pdf
[firstpage_image] =>[orig_patent_app_number] => 11959274
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/959274 | Synergy effect of alloying materials in interconnect structures | Dec 17, 2007 | Issued |
Array
(
[id] => 4965385
[patent_doc_number] => 20080108205
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-08
[patent_title] => 'Semiconductor device and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 12/000599
[patent_app_country] => US
[patent_app_date] => 2007-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 9480
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0108/20080108205.pdf
[firstpage_image] =>[orig_patent_app_number] => 12000599
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/000599 | Semiconductor device and method for manufacturing the same | Dec 13, 2007 | Issued |
Array
(
[id] => 228766
[patent_doc_number] => 07601579
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-10-13
[patent_title] => 'Method of manufacturing semiconductor integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/950675
[patent_app_country] => US
[patent_app_date] => 2007-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 45
[patent_figures_cnt] => 95
[patent_no_of_words] => 14607
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 273
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/601/07601579.pdf
[firstpage_image] =>[orig_patent_app_number] => 11950675
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/950675 | Method of manufacturing semiconductor integrated circuit | Dec 4, 2007 | Issued |
Array
(
[id] => 4825970
[patent_doc_number] => 20080124892
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-29
[patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/943984
[patent_app_country] => US
[patent_app_date] => 2007-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2184
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0124/20080124892.pdf
[firstpage_image] =>[orig_patent_app_number] => 11943984
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/943984 | Method of manufacturing semiconductor device | Nov 20, 2007 | Issued |
Array
(
[id] => 4701796
[patent_doc_number] => 20080061318
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-13
[patent_title] => 'VERTICAL MEMORY DEVICE AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 11/939675
[patent_app_country] => US
[patent_app_date] => 2007-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 6172
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0061/20080061318.pdf
[firstpage_image] =>[orig_patent_app_number] => 11939675
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/939675 | Vertical memory device and method | Nov 13, 2007 | Issued |
Array
(
[id] => 1076915
[patent_doc_number] => 07615428
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-10
[patent_title] => 'Vertical memory device and method'
[patent_app_type] => utility
[patent_app_number] => 11/939686
[patent_app_country] => US
[patent_app_date] => 2007-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 6179
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/615/07615428.pdf
[firstpage_image] =>[orig_patent_app_number] => 11939686
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/939686 | Vertical memory device and method | Nov 13, 2007 | Issued |
Array
(
[id] => 4571508
[patent_doc_number] => 07829446
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-09
[patent_title] => 'Method for dividing wafer, method for manufacturing silicon devices, and method for manufacturing liquid ejecting heads'
[patent_app_type] => utility
[patent_app_number] => 11/937318
[patent_app_country] => US
[patent_app_date] => 2007-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 26
[patent_no_of_words] => 8511
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/829/07829446.pdf
[firstpage_image] =>[orig_patent_app_number] => 11937318
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/937318 | Method for dividing wafer, method for manufacturing silicon devices, and method for manufacturing liquid ejecting heads | Nov 7, 2007 | Issued |
Array
(
[id] => 4768686
[patent_doc_number] => 20080054342
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-06
[patent_title] => 'Memory array having floating gate semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/933728
[patent_app_country] => US
[patent_app_date] => 2007-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3551
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0054/20080054342.pdf
[firstpage_image] =>[orig_patent_app_number] => 11933728
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/933728 | Memory array having floating gate semiconductor device | Oct 31, 2007 | Issued |
Array
(
[id] => 4771970
[patent_doc_number] => 20080057628
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-06
[patent_title] => 'MODIFIED CHIP ATTACH PROCESS'
[patent_app_type] => utility
[patent_app_number] => 11/930760
[patent_app_country] => US
[patent_app_date] => 2007-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4791
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0057/20080057628.pdf
[firstpage_image] =>[orig_patent_app_number] => 11930760
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/930760 | Modified chip attach process | Oct 30, 2007 | Issued |
Array
(
[id] => 4965400
[patent_doc_number] => 20080108220
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-08
[patent_title] => 'INTERCONNECT STRUCTURE WITH A BARRIER-REDUNDANCY FEATURE'
[patent_app_type] => utility
[patent_app_number] => 11/925161
[patent_app_country] => US
[patent_app_date] => 2007-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5194
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0108/20080108220.pdf
[firstpage_image] =>[orig_patent_app_number] => 11925161
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/925161 | Interconnect structure with a barrier-redundancy feature | Oct 25, 2007 | Issued |
Array
(
[id] => 267071
[patent_doc_number] => 07566596
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-07-28
[patent_title] => 'Method of manufacturing a thin film transistor substrate and stripping composition'
[patent_app_type] => utility
[patent_app_number] => 11/875028
[patent_app_country] => US
[patent_app_date] => 2007-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 5696
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/566/07566596.pdf
[firstpage_image] =>[orig_patent_app_number] => 11875028
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/875028 | Method of manufacturing a thin film transistor substrate and stripping composition | Oct 18, 2007 | Issued |
Array
(
[id] => 4652098
[patent_doc_number] => 20080039354
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-14
[patent_title] => 'METHOD OF MANUFACTURING A THIN FILM TRANSISTOR SUBSTRATE AND STRIPPING COMPOSITION'
[patent_app_type] => utility
[patent_app_number] => 11/875035
[patent_app_country] => US
[patent_app_date] => 2007-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5656
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0039/20080039354.pdf
[firstpage_image] =>[orig_patent_app_number] => 11875035
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/875035 | Method of manufacturing a thin film transistor substrate and stripping composition | Oct 18, 2007 | Issued |
Array
(
[id] => 4688251
[patent_doc_number] => 20080032432
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-07
[patent_title] => 'COMPOSITION FOR STRIPPING PHOTORESIST AND METHOD FOR MANUFACTURING THIN TRANSISTOR ARRAY PANEL USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/873791
[patent_app_country] => US
[patent_app_date] => 2007-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 7223
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0032/20080032432.pdf
[firstpage_image] =>[orig_patent_app_number] => 11873791
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/873791 | Composition for stripping photoresist and method for manufacturing thin transistor array panel using the same | Oct 16, 2007 | Issued |