David Nhu

Array ( [id] => 5416465 [patent_doc_number] => 20090042352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'GATE INTERFACE RELAXATION ANNEAL METHOD FOR WAFER PROCESSING WITH POST-IMPLANT DYNAMIC SURFACE ANNEALING' [patent_app_type] => utility [patent_app_number] => 11/835660 [patent_app_country] => US [patent_app_date] => 2007-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20090042352.pdf [firstpage_image] =>[orig_patent_app_number] => 11835660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 285397 [patent_doc_number] => 07550323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-23 [patent_title] => 'Electrical fuse with a thinned fuselink middle portion' [patent_app_type] => utility [patent_app_number] => 11/835800 [patent_app_country] => US [patent_app_date] => 2007-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4297 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/550/07550323.pdf [firstpage_image] =>[orig_patent_app_number] => 11835800 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4899392 [patent_doc_number] => 20080119006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'METHOD FOR MANUFACTURING IMAGE SENSOR' [patent_app_type] => utility [patent_app_number] => 11/831690 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1729 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20080119006.pdf [firstpage_image] =>[orig_patent_app_number] => 11831690 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4909725 [patent_doc_number] => 20080020491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'MAGNETICIALLY LINED CONDUCTORS' [patent_app_type] => utility [patent_app_number] => 11/830810 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3077 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20080020491.pdf [firstpage_image] =>[orig_patent_app_number] => 11830810 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4657688 [patent_doc_number] => 20080026549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'METHODS OF CONTROLLING MORPHOLOGY DURING EPITAXIAL LAYER FORMATION' [patent_app_type] => utility [patent_app_number] => 11/830830 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2496 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20080026549.pdf [firstpage_image] =>[orig_patent_app_number] => 11830830 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4909724 [patent_doc_number] => 20080020490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'METHOD FOR MANUFACTURING FERROELECTRIC MEMORY' [patent_app_type] => utility [patent_app_number] => 11/781290 [patent_app_country] => US [patent_app_date] => 2007-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3618 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20080020490.pdf [firstpage_image] =>[orig_patent_app_number] => 11781290 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 270484 [patent_doc_number] => 07563720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Boron doped shell for MEMS device' [patent_app_type] => utility [patent_app_number] => 11/781470 [patent_app_country] => US [patent_app_date] => 2007-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 4225 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/563/07563720.pdf [firstpage_image] =>[orig_patent_app_number] => 11781470 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5521536 [patent_doc_number] => 20090029517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'Method of Making a Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 11/781320 [patent_app_country] => US [patent_app_date] => 2007-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5938 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20090029517.pdf [firstpage_image] =>[orig_patent_app_number] => 11781320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 220999 [patent_doc_number] => 07608545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-27 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/780970 [patent_app_country] => US [patent_app_date] => 2007-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1963 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/608/07608545.pdf [firstpage_image] =>[orig_patent_app_number] => 11780970 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5230881 [patent_doc_number] => 20070292989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'Semiconductor device and a method of assembling a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/826858 [patent_app_country] => US [patent_app_date] => 2007-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4715 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0292/20070292989.pdf [firstpage_image] =>[orig_patent_app_number] => 11826858 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 243257 [patent_doc_number] => 07588991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Method for fabricating embedded static random access memory' [patent_app_type] => utility [patent_app_number] => 11/779880 [patent_app_country] => US [patent_app_date] => 2007-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5041 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/588/07588991.pdf [firstpage_image] =>[orig_patent_app_number] => 11779880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 307374 [patent_doc_number] => 07531440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Semiconductor laser device, semiconductor laser system, optical pickup module and manufacturing for semiconductor laser system' [patent_app_type] => utility [patent_app_number] => 11/826810 [patent_app_country] => US [patent_app_date] => 2007-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 9079 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/531/07531440.pdf [firstpage_image] =>[orig_patent_app_number] => 11826810 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 211438 [patent_doc_number] => 07622344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-24 [patent_title] => 'Method of manufacturing complementary metal oxide semiconductor transistors' [patent_app_type] => utility [patent_app_number] => 11/779270 [patent_app_country] => US [patent_app_date] => 2007-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 6239 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/622/07622344.pdf [firstpage_image] =>[orig_patent_app_number] => 11779270 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5199223 [patent_doc_number] => 20070298541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'METHOD AND SYSTEM FOR SEALING A SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 11/779185 [patent_app_country] => US [patent_app_date] => 2007-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7317 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20070298541.pdf [firstpage_image] =>[orig_patent_app_number] => 11779185 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 246931 [patent_doc_number] => 07585683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-08 [patent_title] => 'Methods of fabricating ferroelectric devices' [patent_app_type] => utility [patent_app_number] => 11/778880 [patent_app_country] => US [patent_app_date] => 2007-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8633 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/585/07585683.pdf [firstpage_image] =>[orig_patent_app_number] => 11778880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 256289 [patent_doc_number] => 07575962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-18 [patent_title] => 'Fin structure and method of manufacturing fin transistor adopting the fin structure' [patent_app_type] => utility [patent_app_number] => 11/826420 [patent_app_country] => US [patent_app_date] => 2007-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 3196 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/575/07575962.pdf [firstpage_image] =>[orig_patent_app_number] => 11826420 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4893496 [patent_doc_number] => 20080102594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'METHOD FOR FORMING SEMICONDUCTOR MEMORY CAPACITOR WITHOUT CELL-TO-CELL BRIDGES' [patent_app_type] => utility [patent_app_number] => 11/776750 [patent_app_country] => US [patent_app_date] => 2007-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4020 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20080102594.pdf [firstpage_image] =>[orig_patent_app_number] => 11776750 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5010695 [patent_doc_number] => 20070281174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'MULTILAYER BARRIER STACKS AND METHODS OF MAKING MULTILAYER BARRIER STACKS' [patent_app_type] => utility [patent_app_number] => 11/776616 [patent_app_country] => US [patent_app_date] => 2007-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 9391 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20070281174.pdf [firstpage_image] =>[orig_patent_app_number] => 11776616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 296030 [patent_doc_number] => 07541300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-02 [patent_title] => 'Silicon carbide semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/826070 [patent_app_country] => US [patent_app_date] => 2007-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 7410 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/541/07541300.pdf [firstpage_image] =>[orig_patent_app_number] => 11826070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5310291 [patent_doc_number] => 20090017572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'NANOELECTROMECHANICAL TRANSISTORS AND METHODS OF FORMING SAME' [patent_app_type] => utility [patent_app_number] => 11/776160 [patent_app_country] => US [patent_app_date] => 2007-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 91 [patent_figures_cnt] => 91 [patent_no_of_words] => 6493 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20090017572.pdf [firstpage_image] =>[orig_patent_app_number] => 11776160 [rel_patent_id] =>[rel_patent_doc_number] =>)