David Nhu

Array ( [id] => 5247082 [patent_doc_number] => 20070243316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'Method for Conditioning a Microelectronics Device Deposition Chamber' [patent_app_type] => utility [patent_app_number] => 11/759380 [patent_app_country] => US [patent_app_date] => 2007-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3525 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20070243316.pdf [firstpage_image] =>[orig_patent_app_number] => 11759380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13467 [patent_doc_number] => 07807515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-05 [patent_title] => 'Oxide semiconductor, thin-film transistor and method for producing the same' [patent_app_type] => utility [patent_app_number] => 12/086628 [patent_app_country] => US [patent_app_date] => 2007-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3794 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/807/07807515.pdf [firstpage_image] =>[orig_patent_app_number] => 12086628 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5256822 [patent_doc_number] => 20070210454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Structure of Metal Interconnect and Fabrication Method Thereof' [patent_app_type] => utility [patent_app_number] => 11/748472 [patent_app_country] => US [patent_app_date] => 2007-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 3221 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20070210454.pdf [firstpage_image] =>[orig_patent_app_number] => 11748472 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4886722 [patent_doc_number] => 20080261054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Methods of fabricating glass-based substrates and apparatus employing same' [patent_app_type] => utility [patent_app_number] => 11/788570 [patent_app_country] => US [patent_app_date] => 2007-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6097 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20080261054.pdf [firstpage_image] =>[orig_patent_app_number] => 11788570 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5113103 [patent_doc_number] => 20070197018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Wafer-leveled chip packaging structure and method thereof' [patent_app_type] => utility [patent_app_number] => 11/785612 [patent_app_country] => US [patent_app_date] => 2007-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4779 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20070197018.pdf [firstpage_image] =>[orig_patent_app_number] => 11785612 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8277922 [patent_doc_number] => 20120171798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'DAMASCENE PROCESS FOR USE IN FABRICATING SEMICONDUCTOR STRUCTURES HAVING MICRO/NANO GAPS' [patent_app_type] => utility [patent_app_number] => 11/737545 [patent_app_country] => US [patent_app_date] => 2007-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2385 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11737545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5069632 [patent_doc_number] => 20070190734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'ASYMMETRIC SOURCE/DRAIN TRANSISTOR EMPLOYING SELECTIVE EPITAXIAL GROWTH (SEG) LAYER AND METHOD OF FABRICATING SAME' [patent_app_type] => utility [patent_app_number] => 11/735919 [patent_app_country] => US [patent_app_date] => 2007-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4721 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20070190734.pdf [firstpage_image] =>[orig_patent_app_number] => 11735919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5069569 [patent_doc_number] => 20070190671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Manufacturing method of semiconductor integrated circuit device and probe card' [patent_app_type] => utility [patent_app_number] => 11/783778 [patent_app_country] => US [patent_app_date] => 2007-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 17588 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20070190671.pdf [firstpage_image] =>[orig_patent_app_number] => 11783778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 204570 [patent_doc_number] => 07629247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-08 [patent_title] => 'Method of fabricating a self-aligning damascene memory structure' [patent_app_type] => utility [patent_app_number] => 11/786620 [patent_app_country] => US [patent_app_date] => 2007-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 4740 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/629/07629247.pdf [firstpage_image] =>[orig_patent_app_number] => 11786620 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4663725 [patent_doc_number] => 20080254632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'Method for forming a semiconductor structure having nanometer line-width' [patent_app_type] => utility [patent_app_number] => 11/783470 [patent_app_country] => US [patent_app_date] => 2007-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2948 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20080254632.pdf [firstpage_image] =>[orig_patent_app_number] => 11783470 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 359613 [patent_doc_number] => 07485492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Process for manufacturing a non-volatile memory structure via soft lithography' [patent_app_type] => utility [patent_app_number] => 11/697990 [patent_app_country] => US [patent_app_date] => 2007-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 25 [patent_no_of_words] => 5403 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/485/07485492.pdf [firstpage_image] =>[orig_patent_app_number] => 11697990 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 314752 [patent_doc_number] => 07524722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'Resistance type memory device and fabricating method and operating method thereof' [patent_app_type] => utility [patent_app_number] => 11/695780 [patent_app_country] => US [patent_app_date] => 2007-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9813 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/524/07524722.pdf [firstpage_image] =>[orig_patent_app_number] => 11695780 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4685619 [patent_doc_number] => 20080029800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'DYNAMIC RANDOM ACCESS MEMORY' [patent_app_type] => utility [patent_app_number] => 11/696160 [patent_app_country] => US [patent_app_date] => 2007-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1933 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20080029800.pdf [firstpage_image] =>[orig_patent_app_number] => 11696160 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4719484 [patent_doc_number] => 20080242007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'METHOD FOR SELECTIVELY ETCHING PORTIONS OF A LAYER OF MATERIAL BASED UPON A DENSITY OR SIZE OF SEMICONDUCTOR FEATURES LOCATED THEREUNDER' [patent_app_type] => utility [patent_app_number] => 11/694700 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3639 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20080242007.pdf [firstpage_image] =>[orig_patent_app_number] => 11694700 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 564834 [patent_doc_number] => 07465607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-16 [patent_title] => 'Methods of fabrication of lead frame-based semiconductor device packages incorporating at least one land grid array package' [patent_app_type] => utility [patent_app_number] => 11/726283 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4130 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/465/07465607.pdf [firstpage_image] =>[orig_patent_app_number] => 11726283 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5028475 [patent_doc_number] => 20070269922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'Fingerprint detection device and method of its manufacture, and apparatus for forming a protective film' [patent_app_type] => utility [patent_app_number] => 11/725284 [patent_app_country] => US [patent_app_date] => 2007-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10369 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20070269922.pdf [firstpage_image] =>[orig_patent_app_number] => 11725284 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 270483 [patent_doc_number] => 07563719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Dual damascene process' [patent_app_type] => utility [patent_app_number] => 11/724284 [patent_app_country] => US [patent_app_date] => 2007-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2606 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/563/07563719.pdf [firstpage_image] =>[orig_patent_app_number] => 11724284 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6235478 [patent_doc_number] => 20100267182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'WAFER BONDING OF MICRO-ELECTRO MECHANICAL SYSTEMS TO ACTIVE CIRCUITRY' [patent_app_type] => utility [patent_app_number] => 11/686243 [patent_app_country] => US [patent_app_date] => 2007-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6547 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20100267182.pdf [firstpage_image] =>[orig_patent_app_number] => 11686243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5188552 [patent_doc_number] => 20070166860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Active matrix type semicondcutor display device' [patent_app_type] => utility [patent_app_number] => 11/715938 [patent_app_country] => US [patent_app_date] => 2007-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 20803 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20070166860.pdf [firstpage_image] =>[orig_patent_app_number] => 11715938 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4539104 [patent_doc_number] => 07875501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Holding jig, semiconductor wafer grinding method, semiconductor wafer protecting structure and semiconductor wafer grinding method and semiconductor chip fabrication method using the structure' [patent_app_type] => utility [patent_app_number] => 12/282984 [patent_app_country] => US [patent_app_date] => 2007-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 29 [patent_no_of_words] => 21664 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/875/07875501.pdf [firstpage_image] =>[orig_patent_app_number] => 12282984 [rel_patent_id] =>[rel_patent_doc_number] =>)