David Nhu

Array ( [id] => 352624 [patent_doc_number] => 07491645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-17 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/585175 [patent_app_country] => US [patent_app_date] => 2006-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 3256 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/491/07491645.pdf [firstpage_image] =>[orig_patent_app_number] => 11585175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5010964 [patent_doc_number] => 20070281443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'Method of manufacturing devices, positioning method, dicing method and dicing apparatus' [patent_app_type] => utility [patent_app_number] => 11/584630 [patent_app_country] => US [patent_app_date] => 2006-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3974 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20070281443.pdf [firstpage_image] =>[orig_patent_app_number] => 11584630 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 277972 [patent_doc_number] => 07557046 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-07-07 [patent_title] => 'Systems and methods for interconnect metallization using a stop-etch layer' [patent_app_type] => utility [patent_app_number] => 11/584990 [patent_app_country] => US [patent_app_date] => 2006-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 2694 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/557/07557046.pdf [firstpage_image] =>[orig_patent_app_number] => 11584990 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 356193 [patent_doc_number] => 07488629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-10 [patent_title] => 'Fabricating method of an active-matrix organic electroluminescent display panel' [patent_app_type] => utility [patent_app_number] => 11/551250 [patent_app_country] => US [patent_app_date] => 2006-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3591 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/488/07488629.pdf [firstpage_image] =>[orig_patent_app_number] => 11551250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 892019 [patent_doc_number] => 07344985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Nickel alloy silicide including indium and a method of manufacture therefor' [patent_app_type] => utility [patent_app_number] => 11/551374 [patent_app_country] => US [patent_app_date] => 2006-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4807 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/344/07344985.pdf [firstpage_image] =>[orig_patent_app_number] => 11551374 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 582825 [patent_doc_number] => 07445943 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Magnetic tunnel junction memory and method with etch-stop layer' [patent_app_type] => utility [patent_app_number] => 11/584411 [patent_app_country] => US [patent_app_date] => 2006-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 8755 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/445/07445943.pdf [firstpage_image] =>[orig_patent_app_number] => 11584411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 823594 [patent_doc_number] => 07405144 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-29 [patent_title] => 'Method for manufacturing probe card' [patent_app_type] => utility [patent_app_number] => 11/550910 [patent_app_country] => US [patent_app_date] => 2006-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2584 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/405/07405144.pdf [firstpage_image] =>[orig_patent_app_number] => 11550910 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 307332 [patent_doc_number] => 07531398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Methods and devices employing metal layers in gates to introduce channel strain' [patent_app_type] => utility [patent_app_number] => 11/583280 [patent_app_country] => US [patent_app_date] => 2006-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5598 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/531/07531398.pdf [firstpage_image] =>[orig_patent_app_number] => 11583280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5199263 [patent_doc_number] => 20070298581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'METHOD OF MANUFACTURING SUSPENSION STRUCTURE AND CHAMBER' [patent_app_type] => utility [patent_app_number] => 11/550780 [patent_app_country] => US [patent_app_date] => 2006-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 2143 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20070298581.pdf [firstpage_image] =>[orig_patent_app_number] => 11550780 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 565209 [patent_doc_number] => 07465634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-16 [patent_title] => 'Method of forming integrated circuit devices having n-MOSFET and p-MOSFET transistors with elevated and silicided source/drain structures' [patent_app_type] => utility [patent_app_number] => 11/583500 [patent_app_country] => US [patent_app_date] => 2006-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 10259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/465/07465634.pdf [firstpage_image] =>[orig_patent_app_number] => 11583500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 836913 [patent_doc_number] => 07393728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-01 [patent_title] => 'Method of manufacturing an array substrate of a transflective liquid crystal display' [patent_app_type] => utility [patent_app_number] => 11/550040 [patent_app_country] => US [patent_app_date] => 2006-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3145 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/393/07393728.pdf [firstpage_image] =>[orig_patent_app_number] => 11550040 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5154467 [patent_doc_number] => 20070037350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Flash memory cell having reduced floating gate to floating gate coupling' [patent_app_type] => utility [patent_app_number] => 11/582881 [patent_app_country] => US [patent_app_date] => 2006-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3755 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20070037350.pdf [firstpage_image] =>[orig_patent_app_number] => 11582881 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 345086 [patent_doc_number] => 07498273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-03 [patent_title] => 'Formation of high quality dielectric films of silicon dioxide for STI: usage of different siloxane-based precursors for harp II—remote plasma enhanced deposition processes' [patent_app_type] => utility [patent_app_number] => 11/549930 [patent_app_country] => US [patent_app_date] => 2006-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7711 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/498/07498273.pdf [firstpage_image] =>[orig_patent_app_number] => 11549930 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 373286 [patent_doc_number] => 07473589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/549520 [patent_app_country] => US [patent_app_date] => 2006-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 41 [patent_no_of_words] => 5702 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/473/07473589.pdf [firstpage_image] =>[orig_patent_app_number] => 11549520 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5171930 [patent_doc_number] => 20070072363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Method for fabricating transistor gate structures and gate dielectrics thereof' [patent_app_type] => utility [patent_app_number] => 11/549340 [patent_app_country] => US [patent_app_date] => 2006-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6406 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20070072363.pdf [firstpage_image] =>[orig_patent_app_number] => 11549340 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4982963 [patent_doc_number] => 20070087521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Fabrication method of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/546310 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4189 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20070087521.pdf [firstpage_image] =>[orig_patent_app_number] => 11546310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 582982 [patent_doc_number] => 07445957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Method for fabricating wafer level semiconductor package with build-up layer' [patent_app_type] => utility [patent_app_number] => 11/580560 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 4787 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/445/07445957.pdf [firstpage_image] =>[orig_patent_app_number] => 11580560 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 573541 [patent_doc_number] => 07459370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-02 [patent_title] => 'Method of fabricating semiconductor memory device having plurality of storage node electrodes' [patent_app_type] => utility [patent_app_number] => 11/546420 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 30 [patent_no_of_words] => 7682 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/459/07459370.pdf [firstpage_image] =>[orig_patent_app_number] => 11546420 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 836931 [patent_doc_number] => 07393746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-01 [patent_title] => 'Post-silicide spacer removal' [patent_app_type] => utility [patent_app_number] => 11/548870 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2245 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/393/07393746.pdf [firstpage_image] =>[orig_patent_app_number] => 11548870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 573838 [patent_doc_number] => 07462893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Method of fabricating GaN' [patent_app_type] => utility [patent_app_number] => 11/545520 [patent_app_country] => US [patent_app_date] => 2006-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 1793 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/462/07462893.pdf [firstpage_image] =>[orig_patent_app_number] => 11545520 [rel_patent_id] =>[rel_patent_doc_number] =>)