Search

David Nhu

Examiner (ID: 12263, Phone: (571)272-1792 , Office: P/2817 )

Most Active Art Unit
2818
Art Unit(s)
2895, 2818, 2817
Total Applications
2355
Issued Applications
2255
Pending Applications
12
Abandoned Applications
91

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 141657 [patent_doc_number] => 07687322 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-30 [patent_title] => 'Method for removing semiconductor street material' [patent_app_type] => utility [patent_app_number] => 11/548637 [patent_app_country] => US [patent_app_date] => 2006-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 47 [patent_no_of_words] => 5507 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/687/07687322.pdf [firstpage_image] =>[orig_patent_app_number] => 11548637 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/548637
Method for removing semiconductor street material Oct 10, 2006 Issued
Array ( [id] => 4982952 [patent_doc_number] => 20070087510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'SEMICONDUCTOR DEVICES AND MANUFACTURING METHODS OF THE SAME' [patent_app_type] => utility [patent_app_number] => 11/548480 [patent_app_country] => US [patent_app_date] => 2006-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2311 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20070087510.pdf [firstpage_image] =>[orig_patent_app_number] => 11548480 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/548480
Semiconductor devices and manufacturing methods of the same Oct 10, 2006 Issued
Array ( [id] => 4692804 [patent_doc_number] => 20080085575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'DUAL WORK-FUNCTION SINGLE GATE STACK' [patent_app_type] => utility [patent_app_number] => 11/548020 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8940 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20080085575.pdf [firstpage_image] =>[orig_patent_app_number] => 11548020 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/548020
Dual work-function single gate stack Oct 9, 2006 Issued
Array ( [id] => 5034840 [patent_doc_number] => 20070099379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Method of manufacturing a dielectric film in a capacitor' [patent_app_type] => utility [patent_app_number] => 11/544760 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5432 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20070099379.pdf [firstpage_image] =>[orig_patent_app_number] => 11544760 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/544760
Method of manufacturing a dielectric film in a capacitor Oct 9, 2006 Issued
Array ( [id] => 817070 [patent_doc_number] => 07410878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-12 [patent_title] => 'Polysilicon film having smooth surface and method of forming the same' [patent_app_type] => utility [patent_app_number] => 11/539650 [patent_app_country] => US [patent_app_date] => 2006-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 3058 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/410/07410878.pdf [firstpage_image] =>[orig_patent_app_number] => 11539650 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/539650
Polysilicon film having smooth surface and method of forming the same Oct 8, 2006 Issued
Array ( [id] => 348827 [patent_doc_number] => 07494943 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Method for using film formation apparatus' [patent_app_type] => utility [patent_app_number] => 11/543880 [patent_app_country] => US [patent_app_date] => 2006-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 9408 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/494/07494943.pdf [firstpage_image] =>[orig_patent_app_number] => 11543880 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/543880
Method for using film formation apparatus Oct 5, 2006 Issued
Array ( [id] => 817046 [patent_doc_number] => 07410854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-12 [patent_title] => 'Method of making FUSI gate and resulting structure' [patent_app_type] => utility [patent_app_number] => 11/543410 [patent_app_country] => US [patent_app_date] => 2006-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4319 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/410/07410854.pdf [firstpage_image] =>[orig_patent_app_number] => 11543410 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/543410
Method of making FUSI gate and resulting structure Oct 4, 2006 Issued
Array ( [id] => 5188705 [patent_doc_number] => 20070167014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'CMP method providing reduced thickness variations' [patent_app_type] => utility [patent_app_number] => 11/543200 [patent_app_country] => US [patent_app_date] => 2006-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4670 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20070167014.pdf [firstpage_image] =>[orig_patent_app_number] => 11543200 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/543200
CMP method providing reduced thickness variations Oct 4, 2006 Issued
Array ( [id] => 4692816 [patent_doc_number] => 20080085587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'Epitaxial silicon growth' [patent_app_type] => utility [patent_app_number] => 11/543560 [patent_app_country] => US [patent_app_date] => 2006-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8073 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20080085587.pdf [firstpage_image] =>[orig_patent_app_number] => 11543560 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/543560
Epitaxial silicon growth Oct 3, 2006 Issued
Array ( [id] => 263685 [patent_doc_number] => 07569449 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-08-04 [patent_title] => 'Processes providing high and low threshold p-type and n-type transistors' [patent_app_type] => utility [patent_app_number] => 11/543580 [patent_app_country] => US [patent_app_date] => 2006-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4154 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/569/07569449.pdf [firstpage_image] =>[orig_patent_app_number] => 11543580 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/543580
Processes providing high and low threshold p-type and n-type transistors Oct 2, 2006 Issued
Array ( [id] => 4944134 [patent_doc_number] => 20080081459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Dual layer dielectric stack for microelectronics having thick metal lines' [patent_app_type] => utility [patent_app_number] => 11/540350 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2782 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20080081459.pdf [firstpage_image] =>[orig_patent_app_number] => 11540350 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/540350
Dual layer dielectric stack for microelectronics having thick metal lines Sep 28, 2006 Issued
Array ( [id] => 53036 [patent_doc_number] => 07772108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Interconnection structures for semiconductor devices and methods of forming the same' [patent_app_type] => utility [patent_app_number] => 11/541027 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 52 [patent_no_of_words] => 9278 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/772/07772108.pdf [firstpage_image] =>[orig_patent_app_number] => 11541027 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/541027
Interconnection structures for semiconductor devices and methods of forming the same Sep 28, 2006 Issued
Array ( [id] => 323013 [patent_doc_number] => 07518246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-14 [patent_title] => 'Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics' [patent_app_type] => utility [patent_app_number] => 11/528776 [patent_app_country] => US [patent_app_date] => 2006-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8099 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/518/07518246.pdf [firstpage_image] =>[orig_patent_app_number] => 11528776 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/528776
Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics Sep 27, 2006 Issued
Array ( [id] => 211422 [patent_doc_number] => 07622328 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-24 [patent_title] => 'Processing method of wafer' [patent_app_type] => utility [patent_app_number] => 11/529137 [patent_app_country] => US [patent_app_date] => 2006-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 23 [patent_no_of_words] => 5845 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/622/07622328.pdf [firstpage_image] =>[orig_patent_app_number] => 11529137 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/529137
Processing method of wafer Sep 27, 2006 Issued
Array ( [id] => 373694 [patent_doc_number] => 07473998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Method for forming bump protective collars on a bumped wafer' [patent_app_type] => utility [patent_app_number] => 11/524894 [patent_app_country] => US [patent_app_date] => 2006-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1708 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/473/07473998.pdf [firstpage_image] =>[orig_patent_app_number] => 11524894 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/524894
Method for forming bump protective collars on a bumped wafer Sep 21, 2006 Issued
Array ( [id] => 356250 [patent_doc_number] => 07488686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-10 [patent_title] => 'Electrochemical fabrication methods including use of surface treatments to reduce overplating and/or planarization during formation of multi-layer three-dimensional structures' [patent_app_type] => utility [patent_app_number] => 11/523206 [patent_app_country] => US [patent_app_date] => 2006-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 95 [patent_no_of_words] => 20437 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/488/07488686.pdf [firstpage_image] =>[orig_patent_app_number] => 11523206 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/523206
Electrochemical fabrication methods including use of surface treatments to reduce overplating and/or planarization during formation of multi-layer three-dimensional structures Sep 18, 2006 Issued
Array ( [id] => 6561351 [patent_doc_number] => 20100059733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'LED Structure' [patent_app_type] => utility [patent_app_number] => 12/441204 [patent_app_country] => US [patent_app_date] => 2006-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7297 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20100059733.pdf [firstpage_image] =>[orig_patent_app_number] => 12441204 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/441204
LED structure Sep 12, 2006 Issued
Array ( [id] => 6352883 [patent_doc_number] => 20100022102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'LASER ANNEALING METHOD AND DEVICE' [patent_app_type] => utility [patent_app_number] => 11/916687 [patent_app_country] => US [patent_app_date] => 2006-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9810 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20100022102.pdf [firstpage_image] =>[orig_patent_app_number] => 11916687 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/916687
Laser annealing method and device Sep 11, 2006 Issued
Array ( [id] => 5364830 [patent_doc_number] => 20090302389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH DIFFERENT METALLIC GATES' [patent_app_type] => utility [patent_app_number] => 12/066707 [patent_app_country] => US [patent_app_date] => 2006-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3376 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20090302389.pdf [firstpage_image] =>[orig_patent_app_number] => 12066707 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/066707
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH DIFFERENT METALLIC GATES Sep 10, 2006 Abandoned
Array ( [id] => 573813 [patent_doc_number] => 07459388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-02 [patent_title] => 'Methods of forming dual-damascene interconnect structures using adhesion layers having high internal compressive stresses' [patent_app_type] => utility [patent_app_number] => 11/470320 [patent_app_country] => US [patent_app_date] => 2006-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2084 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/459/07459388.pdf [firstpage_image] =>[orig_patent_app_number] => 11470320 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/470320
Methods of forming dual-damascene interconnect structures using adhesion layers having high internal compressive stresses Sep 5, 2006 Issued
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