
David R. Morris
Examiner (ID: 19201, Phone: (571)270-3595 , Office: P/3659 )
| Most Active Art Unit | 3659 |
| Art Unit(s) | 3659, 3616, OPQA |
| Total Applications | 693 |
| Issued Applications | 527 |
| Pending Applications | 85 |
| Abandoned Applications | 97 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11460124
[patent_doc_number] => 20170054029
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-23
[patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/231061
[patent_app_country] => US
[patent_app_date] => 2016-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 72
[patent_figures_cnt] => 72
[patent_no_of_words] => 63794
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15231061
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/231061 | Manufacturing method of semiconductor device | Aug 7, 2016 | Issued |
Array
(
[id] => 11439138
[patent_doc_number] => 20170040159
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-09
[patent_title] => 'SELF-LIMITING AND SATURATING CHEMICAL VAPOR DEPOSITION OF A SILICON BILAYER AND ALD'
[patent_app_type] => utility
[patent_app_number] => 15/230218
[patent_app_country] => US
[patent_app_date] => 2016-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6806
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15230218
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/230218 | Self-limiting and saturating chemical vapor deposition of a silicon bilayer and ALD | Aug 4, 2016 | Issued |
Array
(
[id] => 11273726
[patent_doc_number] => 20160336272
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-17
[patent_title] => 'Semiconductor Device Having Gold Metallization Structures'
[patent_app_type] => utility
[patent_app_number] => 15/220161
[patent_app_country] => US
[patent_app_date] => 2016-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4788
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15220161
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/220161 | Semiconductor Device Having Gold Metallization Structures | Jul 25, 2016 | Abandoned |
Array
(
[id] => 11132271
[patent_doc_number] => 20160329247
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-10
[patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/217032
[patent_app_country] => US
[patent_app_date] => 2016-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6565
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15217032
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/217032 | Method of manufacturing semiconductor device by applying molding layer in substrate groove | Jul 21, 2016 | Issued |
Array
(
[id] => 11111135
[patent_doc_number] => 20160308105
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-10-20
[patent_title] => 'LAMINATED ELECTRICAL TRACE WITHIN AN LED INTERCONNECT'
[patent_app_type] => utility
[patent_app_number] => 15/195907
[patent_app_country] => US
[patent_app_date] => 2016-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4541
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15195907
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/195907 | LAMINATED ELECTRICAL TRACE WITHIN AN LED INTERCONNECT | Jun 27, 2016 | Abandoned |
Array
(
[id] => 11386084
[patent_doc_number] => 20170012139
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-12
[patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 15/193564
[patent_app_country] => US
[patent_app_date] => 2016-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 45
[patent_figures_cnt] => 45
[patent_no_of_words] => 45064
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193564
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/193564 | Semiconductor device including transistor having low parasitic capacitance | Jun 26, 2016 | Issued |
Array
(
[id] => 13724061
[patent_doc_number] => 20170372986
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-28
[patent_title] => LDMOS Transistor and Method
[patent_app_type] => utility
[patent_app_number] => 15/192283
[patent_app_country] => US
[patent_app_date] => 2016-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8294
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -29
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192283
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/192283 | LDMOS transistor and method | Jun 23, 2016 | Issued |
Array
(
[id] => 14094039
[patent_doc_number] => 10242932
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-03-26
[patent_title] => LDMOS transistor and method
[patent_app_type] => utility
[patent_app_number] => 15/191989
[patent_app_country] => US
[patent_app_date] => 2016-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 7368
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15191989
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/191989 | LDMOS transistor and method | Jun 23, 2016 | Issued |
Array
(
[id] => 13057475
[patent_doc_number] => 10050139
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-08-14
[patent_title] => Semiconductor device including a LDMOS transistor and method
[patent_app_type] => utility
[patent_app_number] => 15/191937
[patent_app_country] => US
[patent_app_date] => 2016-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 20
[patent_no_of_words] => 8630
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15191937
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/191937 | Semiconductor device including a LDMOS transistor and method | Jun 23, 2016 | Issued |
Array
(
[id] => 13724061
[patent_doc_number] => 20170372986
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-28
[patent_title] => LDMOS Transistor and Method
[patent_app_type] => utility
[patent_app_number] => 15/192283
[patent_app_country] => US
[patent_app_date] => 2016-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8294
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -29
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192283
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/192283 | LDMOS transistor and method | Jun 23, 2016 | Issued |
Array
(
[id] => 13724061
[patent_doc_number] => 20170372986
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-28
[patent_title] => LDMOS Transistor and Method
[patent_app_type] => utility
[patent_app_number] => 15/192283
[patent_app_country] => US
[patent_app_date] => 2016-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8294
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -29
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192283
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/192283 | LDMOS transistor and method | Jun 23, 2016 | Issued |
Array
(
[id] => 13723993
[patent_doc_number] => 20170372952
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-28
[patent_title] => SUBSTRATE AND METHOD INCLUDING FORMING A VIA COMPRISING A CONDUCTIVE LINER LAYER AND CONDUCTIVE PLUG HAVING DIFFERENT MICROSTRUCTURES
[patent_app_type] => utility
[patent_app_number] => 15/192146
[patent_app_country] => US
[patent_app_date] => 2016-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4117
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -25
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192146
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/192146 | Substrate and method including forming a via comprising a conductive liner layer and conductive plug having different microstructures | Jun 23, 2016 | Issued |
Array
(
[id] => 13724061
[patent_doc_number] => 20170372986
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-28
[patent_title] => LDMOS Transistor and Method
[patent_app_type] => utility
[patent_app_number] => 15/192283
[patent_app_country] => US
[patent_app_date] => 2016-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8294
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -29
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192283
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/192283 | LDMOS transistor and method | Jun 23, 2016 | Issued |
Array
(
[id] => 11110914
[patent_doc_number] => 20160307885
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-10-20
[patent_title] => 'Semiconductor Device Including a Diode at Least Partly Arranged in a Trench'
[patent_app_type] => utility
[patent_app_number] => 15/189031
[patent_app_country] => US
[patent_app_date] => 2016-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7123
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15189031
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/189031 | Semiconductor device including a diode at least partly arranged in a trench | Jun 21, 2016 | Issued |
Array
(
[id] => 14348533
[patent_doc_number] => 20190156239
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-23
[patent_title] => FIDELITY ESTIMATION FOR QUANTUM COMPUTING SYSTEMS
[patent_app_type] => utility
[patent_app_number] => 16/301863
[patent_app_country] => US
[patent_app_date] => 2016-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7719
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16301863
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/301863 | Fidelity estimation for quantum computing systems | May 16, 2016 | Issued |
Array
(
[id] => 11972778
[patent_doc_number] => 20170276932
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-09-28
[patent_title] => 'OPTICAL ELEMENT MODULE AND METHOD FOR PRODUCING OPTICAL ELEMENT MODULE'
[patent_app_type] => utility
[patent_app_number] => 15/508596
[patent_app_country] => US
[patent_app_date] => 2016-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6550
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15508596
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/508596 | OPTICAL ELEMENT MODULE AND METHOD FOR PRODUCING OPTICAL ELEMENT MODULE | May 9, 2016 | Abandoned |
Array
(
[id] => 15791723
[patent_doc_number] => 10629593
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-04-21
[patent_title] => Formation of semiconductor device with resistors having different resistances
[patent_app_type] => utility
[patent_app_number] => 15/134272
[patent_app_country] => US
[patent_app_date] => 2016-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 17
[patent_no_of_words] => 4531
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 239
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15134272
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/134272 | Formation of semiconductor device with resistors having different resistances | Apr 19, 2016 | Issued |
Array
(
[id] => 11981276
[patent_doc_number] => 20170285430
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-10-05
[patent_title] => 'Array Substrate and Manufacturing Method Thereof, Display Panel and Display Device'
[patent_app_type] => utility
[patent_app_number] => 15/508319
[patent_app_country] => US
[patent_app_date] => 2016-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6695
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15508319
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/508319 | Array Substrate and Manufacturing Method Thereof, Display Panel and Display Device | Mar 23, 2016 | Abandoned |
Array
(
[id] => 11592726
[patent_doc_number] => 20170117138
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-04-27
[patent_title] => 'METHOD OF PREPARATION OF III-V COMPOUND LAYER ON LARGE AREA SI INSULATING SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 15/067192
[patent_app_country] => US
[patent_app_date] => 2016-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2445
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15067192
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/067192 | Method of preparation of III-V compound layer on large area Si insulating substrate | Mar 10, 2016 | Issued |
Array
(
[id] => 11439210
[patent_doc_number] => 20170040231
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-09
[patent_title] => 'METHOD FOR PROCESSING SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 15/066667
[patent_app_country] => US
[patent_app_date] => 2016-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5601
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15066667
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/066667 | Method for processing substrate including forming a film on a silicon-containing surface of the substrate to prevent resist from extruding from the substrate during an imprinting process | Mar 9, 2016 | Issued |