Search

David R. Hudspeth

Supervisory Patent Examiner (ID: 19114, Phone: (571)272-7843 , Office: P/2657 )

Most Active Art Unit
2504
Art Unit(s)
2651, 2509, 2641, 2657, 2504, 2626, 2681, 2741
Total Applications
1592
Issued Applications
1465
Pending Applications
21
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3630217 [patent_doc_number] => 05608341 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-04 [patent_title] => 'Electrical circuit for setting internal chip functions without dedicated configuration pins' [patent_app_type] => 1 [patent_app_number] => 8/437621 [patent_app_country] => US [patent_app_date] => 1995-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4595 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/608/05608341.pdf [firstpage_image] =>[orig_patent_app_number] => 437621 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/437621
Electrical circuit for setting internal chip functions without dedicated configuration pins May 8, 1995 Issued
Array ( [id] => 3595999 [patent_doc_number] => 05568064 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Bidirectional transmission line driver/receiver' [patent_app_type] => 1 [patent_app_number] => 8/438134 [patent_app_country] => US [patent_app_date] => 1995-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9052 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/568/05568064.pdf [firstpage_image] =>[orig_patent_app_number] => 438134 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/438134
Bidirectional transmission line driver/receiver May 7, 1995 Issued
Array ( [id] => 3669858 [patent_doc_number] => 05598107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Current switching circuit having reduced current noise operation' [patent_app_type] => 1 [patent_app_number] => 8/435602 [patent_app_country] => US [patent_app_date] => 1995-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1924 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598107.pdf [firstpage_image] =>[orig_patent_app_number] => 435602 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/435602
Current switching circuit having reduced current noise operation May 4, 1995 Issued
Array ( [id] => 3576958 [patent_doc_number] => 05539330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'Interconnect bus system for use with self-configuring electronic circuit modules' [patent_app_type] => 1 [patent_app_number] => 8/433723 [patent_app_country] => US [patent_app_date] => 1995-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5312 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/539/05539330.pdf [firstpage_image] =>[orig_patent_app_number] => 433723 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/433723
Interconnect bus system for use with self-configuring electronic circuit modules May 2, 1995 Issued
08/431394 SELECTIVE CURRENT LIMITS IN SEMICONDUCTOR DEVICES Apr 27, 1995 Abandoned
Array ( [id] => 3617311 [patent_doc_number] => 05565758 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'Mapping of gate arrays' [patent_app_type] => 1 [patent_app_number] => 8/429701 [patent_app_country] => US [patent_app_date] => 1995-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3031 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/565/05565758.pdf [firstpage_image] =>[orig_patent_app_number] => 429701 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/429701
Mapping of gate arrays Apr 26, 1995 Issued
Array ( [id] => 3630244 [patent_doc_number] => 05608343 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-04 [patent_title] => 'Circuit for varying read timing' [patent_app_type] => 1 [patent_app_number] => 8/429820 [patent_app_country] => US [patent_app_date] => 1995-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 3861 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/608/05608343.pdf [firstpage_image] =>[orig_patent_app_number] => 429820 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/429820
Circuit for varying read timing Apr 26, 1995 Issued
Array ( [id] => 3525605 [patent_doc_number] => 05530378 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Cross point interconnect structure with reduced area' [patent_app_type] => 1 [patent_app_number] => 8/430207 [patent_app_country] => US [patent_app_date] => 1995-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5190 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530378.pdf [firstpage_image] =>[orig_patent_app_number] => 430207 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/430207
Cross point interconnect structure with reduced area Apr 25, 1995 Issued
Array ( [id] => 3530610 [patent_doc_number] => 05528169 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-18 [patent_title] => 'Method and structure for providing a flip flop circuit with a configurable data input path' [patent_app_type] => 1 [patent_app_number] => 8/430510 [patent_app_country] => US [patent_app_date] => 1995-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4056 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/528/05528169.pdf [firstpage_image] =>[orig_patent_app_number] => 430510 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/430510
Method and structure for providing a flip flop circuit with a configurable data input path Apr 25, 1995 Issued
Array ( [id] => 3516374 [patent_doc_number] => 05563527 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-08 [patent_title] => 'Power-managed sense amplifier for programmable logic device' [patent_app_type] => 1 [patent_app_number] => 8/426305 [patent_app_country] => US [patent_app_date] => 1995-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2204 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/563/05563527.pdf [firstpage_image] =>[orig_patent_app_number] => 426305 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/426305
Power-managed sense amplifier for programmable logic device Apr 20, 1995 Issued
Array ( [id] => 3661072 [patent_doc_number] => 05623216 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Output buffer current slew rate control integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/425000 [patent_app_country] => US [patent_app_date] => 1995-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4765 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623216.pdf [firstpage_image] =>[orig_patent_app_number] => 425000 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/425000
Output buffer current slew rate control integrated circuit Apr 18, 1995 Issued
Array ( [id] => 3424488 [patent_doc_number] => 05479112 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'Logic gate with matched output rise and fall times and method of construction' [patent_app_type] => 1 [patent_app_number] => 8/424765 [patent_app_country] => US [patent_app_date] => 1995-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4273 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 367 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/479/05479112.pdf [firstpage_image] =>[orig_patent_app_number] => 424765 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/424765
Logic gate with matched output rise and fall times and method of construction Apr 18, 1995 Issued
08/423770 NULL CONVENTION INTERFACE CIRCUITS Apr 17, 1995 Abandoned
Array ( [id] => 3560487 [patent_doc_number] => 05543731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'Dynamic and preset static multiplexer in front of latch circuit for use in static circuits' [patent_app_type] => 1 [patent_app_number] => 8/414412 [patent_app_country] => US [patent_app_date] => 1995-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1816 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/543/05543731.pdf [firstpage_image] =>[orig_patent_app_number] => 414412 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/414412
Dynamic and preset static multiplexer in front of latch circuit for use in static circuits Mar 30, 1995 Issued
Array ( [id] => 3597851 [patent_doc_number] => 05521538 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-28 [patent_title] => 'Adiabatic logic' [patent_app_type] => 1 [patent_app_number] => 8/413658 [patent_app_country] => US [patent_app_date] => 1995-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3991 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/521/05521538.pdf [firstpage_image] =>[orig_patent_app_number] => 413658 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/413658
Adiabatic logic Mar 29, 1995 Issued
Array ( [id] => 3555786 [patent_doc_number] => 05572148 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory' [patent_app_type] => 1 [patent_app_number] => 8/408510 [patent_app_country] => US [patent_app_date] => 1995-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 9346 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/572/05572148.pdf [firstpage_image] =>[orig_patent_app_number] => 408510 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/408510
Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory Mar 21, 1995 Issued
Array ( [id] => 3628717 [patent_doc_number] => 05612635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'High noise-margin TTL buffer circuit capable of operation with wide variation in the power supply voltage' [patent_app_type] => 1 [patent_app_number] => 8/408514 [patent_app_country] => US [patent_app_date] => 1995-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1991 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/612/05612635.pdf [firstpage_image] =>[orig_patent_app_number] => 408514 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/408514
High noise-margin TTL buffer circuit capable of operation with wide variation in the power supply voltage Mar 21, 1995 Issued
Array ( [id] => 3512483 [patent_doc_number] => 05570040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-29 [patent_title] => 'Programmable logic array integrated circuit incorporating a first-in first-out memory' [patent_app_type] => 1 [patent_app_number] => 8/408504 [patent_app_country] => US [patent_app_date] => 1995-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6280 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/570/05570040.pdf [firstpage_image] =>[orig_patent_app_number] => 408504 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/408504
Programmable logic array integrated circuit incorporating a first-in first-out memory Mar 21, 1995 Issued
Array ( [id] => 3707565 [patent_doc_number] => 05646554 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Method and apparatus for selective clocking using a Muller-C element' [patent_app_type] => 1 [patent_app_number] => 8/406316 [patent_app_country] => US [patent_app_date] => 1995-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 4633 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646554.pdf [firstpage_image] =>[orig_patent_app_number] => 406316 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/406316
Method and apparatus for selective clocking using a Muller-C element Mar 15, 1995 Issued
Array ( [id] => 3530568 [patent_doc_number] => 05528166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-18 [patent_title] => 'Pulse controlled impedance compensated output buffer' [patent_app_type] => 1 [patent_app_number] => 8/403410 [patent_app_country] => US [patent_app_date] => 1995-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5863 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/528/05528166.pdf [firstpage_image] =>[orig_patent_app_number] => 403410 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/403410
Pulse controlled impedance compensated output buffer Mar 13, 1995 Issued
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