
David R. Hudspeth
Supervisory Patent Examiner (ID: 19114, Phone: (571)272-7843 , Office: P/2657 )
| Most Active Art Unit | 2504 |
| Art Unit(s) | 2651, 2509, 2641, 2657, 2504, 2626, 2681, 2741 |
| Total Applications | 1592 |
| Issued Applications | 1465 |
| Pending Applications | 21 |
| Abandoned Applications | 105 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3630217
[patent_doc_number] => 05608341
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-04
[patent_title] => 'Electrical circuit for setting internal chip functions without dedicated configuration pins'
[patent_app_type] => 1
[patent_app_number] => 8/437621
[patent_app_country] => US
[patent_app_date] => 1995-05-09
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[pdf_file] => patents/05/608/05608341.pdf
[firstpage_image] =>[orig_patent_app_number] => 437621
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/437621 | Electrical circuit for setting internal chip functions without dedicated configuration pins | May 8, 1995 | Issued |
Array
(
[id] => 3595999
[patent_doc_number] => 05568064
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-22
[patent_title] => 'Bidirectional transmission line driver/receiver'
[patent_app_type] => 1
[patent_app_number] => 8/438134
[patent_app_country] => US
[patent_app_date] => 1995-05-08
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[firstpage_image] =>[orig_patent_app_number] => 438134
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/438134 | Bidirectional transmission line driver/receiver | May 7, 1995 | Issued |
Array
(
[id] => 3669858
[patent_doc_number] => 05598107
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-28
[patent_title] => 'Current switching circuit having reduced current noise operation'
[patent_app_type] => 1
[patent_app_number] => 8/435602
[patent_app_country] => US
[patent_app_date] => 1995-05-05
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[firstpage_image] =>[orig_patent_app_number] => 435602
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/435602 | Current switching circuit having reduced current noise operation | May 4, 1995 | Issued |
Array
(
[id] => 3576958
[patent_doc_number] => 05539330
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-23
[patent_title] => 'Interconnect bus system for use with self-configuring electronic circuit modules'
[patent_app_type] => 1
[patent_app_number] => 8/433723
[patent_app_country] => US
[patent_app_date] => 1995-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => patents/05/539/05539330.pdf
[firstpage_image] =>[orig_patent_app_number] => 433723
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/433723 | Interconnect bus system for use with self-configuring electronic circuit modules | May 2, 1995 | Issued |
| 08/431394 | SELECTIVE CURRENT LIMITS IN SEMICONDUCTOR DEVICES | Apr 27, 1995 | Abandoned |
Array
(
[id] => 3617311
[patent_doc_number] => 05565758
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[patent_issue_date] => 1996-10-15
[patent_title] => 'Mapping of gate arrays'
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[patent_app_number] => 8/429701
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Array
(
[id] => 3630244
[patent_doc_number] => 05608343
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[patent_issue_date] => 1997-03-04
[patent_title] => 'Circuit for varying read timing'
[patent_app_type] => 1
[patent_app_number] => 8/429820
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[firstpage_image] =>[orig_patent_app_number] => 429820
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/429820 | Circuit for varying read timing | Apr 26, 1995 | Issued |
Array
(
[id] => 3525605
[patent_doc_number] => 05530378
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[patent_issue_date] => 1996-06-25
[patent_title] => 'Cross point interconnect structure with reduced area'
[patent_app_type] => 1
[patent_app_number] => 8/430207
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[firstpage_image] =>[orig_patent_app_number] => 430207
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/430207 | Cross point interconnect structure with reduced area | Apr 25, 1995 | Issued |
Array
(
[id] => 3530610
[patent_doc_number] => 05528169
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[patent_kind] => NA
[patent_issue_date] => 1996-06-18
[patent_title] => 'Method and structure for providing a flip flop circuit with a configurable data input path'
[patent_app_type] => 1
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[pdf_file] => patents/05/528/05528169.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/430510 | Method and structure for providing a flip flop circuit with a configurable data input path | Apr 25, 1995 | Issued |
Array
(
[id] => 3516374
[patent_doc_number] => 05563527
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-08
[patent_title] => 'Power-managed sense amplifier for programmable logic device'
[patent_app_type] => 1
[patent_app_number] => 8/426305
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/426305 | Power-managed sense amplifier for programmable logic device | Apr 20, 1995 | Issued |
Array
(
[id] => 3661072
[patent_doc_number] => 05623216
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[patent_kind] => NA
[patent_issue_date] => 1997-04-22
[patent_title] => 'Output buffer current slew rate control integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/425000
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[firstpage_image] =>[orig_patent_app_number] => 425000
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/425000 | Output buffer current slew rate control integrated circuit | Apr 18, 1995 | Issued |
Array
(
[id] => 3424488
[patent_doc_number] => 05479112
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-26
[patent_title] => 'Logic gate with matched output rise and fall times and method of construction'
[patent_app_type] => 1
[patent_app_number] => 8/424765
[patent_app_country] => US
[patent_app_date] => 1995-04-19
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/424765 | Logic gate with matched output rise and fall times and method of construction | Apr 18, 1995 | Issued |
| 08/423770 | NULL CONVENTION INTERFACE CIRCUITS | Apr 17, 1995 | Abandoned |
Array
(
[id] => 3560487
[patent_doc_number] => 05543731
[patent_country] => US
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[patent_issue_date] => 1996-08-06
[patent_title] => 'Dynamic and preset static multiplexer in front of latch circuit for use in static circuits'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/414412 | Dynamic and preset static multiplexer in front of latch circuit for use in static circuits | Mar 30, 1995 | Issued |
Array
(
[id] => 3597851
[patent_doc_number] => 05521538
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[patent_title] => 'Adiabatic logic'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/413658 | Adiabatic logic | Mar 29, 1995 | Issued |
Array
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Array
(
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[patent_title] => 'High noise-margin TTL buffer circuit capable of operation with wide variation in the power supply voltage'
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Array
(
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/403410 | Pulse controlled impedance compensated output buffer | Mar 13, 1995 | Issued |