David R. Hudspeth

Array ( [id] => 3629049 [patent_doc_number] => 05602494 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Bi-directional programmable I/O cell' [patent_app_type] => 1 [patent_app_number] => 8/401604 [patent_app_country] => US [patent_app_date] => 1995-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4784 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/602/05602494.pdf [firstpage_image] =>[orig_patent_app_number] => 401604 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3562880 [patent_doc_number] => 05502406 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Low power level shift circuit and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/399004 [patent_app_country] => US [patent_app_date] => 1995-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4184 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502406.pdf [firstpage_image] =>[orig_patent_app_number] => 399004 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3593962 [patent_doc_number] => 05517136 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'Opportunistic time-borrowing domino logic' [patent_app_type] => 1 [patent_app_number] => 8/398123 [patent_app_country] => US [patent_app_date] => 1995-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 5564 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/517/05517136.pdf [firstpage_image] =>[orig_patent_app_number] => 398123 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3586850 [patent_doc_number] => 05498977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-12 [patent_title] => 'Output driver having process, voltage and temperature compensation for delay and risetime' [patent_app_type] => 1 [patent_app_number] => 8/397812 [patent_app_country] => US [patent_app_date] => 1995-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2877 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/498/05498977.pdf [firstpage_image] =>[orig_patent_app_number] => 397812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3502483 [patent_doc_number] => 05532625 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-02 [patent_title] => 'Wave propagation logic' [patent_app_type] => 1 [patent_app_number] => 8/397419 [patent_app_country] => US [patent_app_date] => 1995-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9124 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/532/05532625.pdf [firstpage_image] =>[orig_patent_app_number] => 397419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3558010 [patent_doc_number] => 05493240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-20 [patent_title] => 'Static combinatorial logic circuits for reversible computation' [patent_app_type] => 1 [patent_app_number] => 8/397007 [patent_app_country] => US [patent_app_date] => 1995-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 2996 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/493/05493240.pdf [firstpage_image] =>[orig_patent_app_number] => 397007 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3856692 [patent_doc_number] => RE035745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Device for generating a reference voltage for a switching circuit including a capacitive bootstrap circuit' [patent_app_type] => 2 [patent_app_number] => 8/395135 [patent_app_country] => US [patent_app_date] => 1995-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2418 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/035/RE035745.pdf [firstpage_image] =>[orig_patent_app_number] => 395135 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3737460 [patent_doc_number] => 05694059 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Buffer of fine connection structure for connecting an atom level circuit and a general semiconductor circuit' [patent_app_type] => 1 [patent_app_number] => 8/383843 [patent_app_country] => US [patent_app_date] => 1995-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 4838 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694059.pdf [firstpage_image] =>[orig_patent_app_number] => 383843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3499912 [patent_doc_number] => 05508635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-16 [patent_title] => 'Reduced noise data output buffer with output level regulation' [patent_app_type] => 1 [patent_app_number] => 8/383005 [patent_app_country] => US [patent_app_date] => 1995-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1971 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/508/05508635.pdf [firstpage_image] =>[orig_patent_app_number] => 383005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3477618 [patent_doc_number] => 05477167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-19 [patent_title] => 'Programmable application specific integrated circuit using logic circuits to program antifuses therein' [patent_app_type] => 1 [patent_app_number] => 8/379061 [patent_app_country] => US [patent_app_date] => 1995-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 8086 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/477/05477167.pdf [firstpage_image] =>[orig_patent_app_number] => 379061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3607970 [patent_doc_number] => 05578939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-26 [patent_title] => 'Bidirectional transmission line driver/receiver' [patent_app_type] => 1 [patent_app_number] => 8/376708 [patent_app_country] => US [patent_app_date] => 1995-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6849 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/578/05578939.pdf [firstpage_image] =>[orig_patent_app_number] => 376708 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3566822 [patent_doc_number] => 05525914 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-11 [patent_title] => 'CMOS driver circuit' [patent_app_type] => 1 [patent_app_number] => 8/376704 [patent_app_country] => US [patent_app_date] => 1995-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3592 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/525/05525914.pdf [firstpage_image] =>[orig_patent_app_number] => 376704 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3577005 [patent_doc_number] => 05539333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'CMOS receiver circuit' [patent_app_type] => 1 [patent_app_number] => 8/376705 [patent_app_country] => US [patent_app_date] => 1995-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3425 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/539/05539333.pdf [firstpage_image] =>[orig_patent_app_number] => 376705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3597671 [patent_doc_number] => 05521527 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-28 [patent_title] => 'Semiconductor integrated circuits with power reduction mechanism' [patent_app_type] => 1 [patent_app_number] => 8/374990 [patent_app_country] => US [patent_app_date] => 1995-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 15379 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/521/05521527.pdf [firstpage_image] =>[orig_patent_app_number] => 374990 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3593903 [patent_doc_number] => 05517132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'Logic synthesis method and semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/375413 [patent_app_country] => US [patent_app_date] => 1995-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 32 [patent_no_of_words] => 8594 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/517/05517132.pdf [firstpage_image] =>[orig_patent_app_number] => 375413 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3543063 [patent_doc_number] => 05495184 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'High-speed low-power CMOS PECL I/O transmitter' [patent_app_type] => 1 [patent_app_number] => 8/371724 [patent_app_country] => US [patent_app_date] => 1995-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5664 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 445 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/495/05495184.pdf [firstpage_image] =>[orig_patent_app_number] => 371724 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3572143 [patent_doc_number] => 05485107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Backplane driver circuit' [patent_app_type] => 1 [patent_app_number] => 8/370115 [patent_app_country] => US [patent_app_date] => 1995-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2635 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/485/05485107.pdf [firstpage_image] =>[orig_patent_app_number] => 370115 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3916973 [patent_doc_number] => 05751902 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Adaptive prediction filter using block floating point format and minimal recursive recomputations' [patent_app_type] => 1 [patent_app_number] => 8/362514 [patent_app_country] => US [patent_app_date] => 1995-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6074 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751902.pdf [firstpage_image] =>[orig_patent_app_number] => 362514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3562817 [patent_doc_number] => 05502402 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'FPGA architecture based on a single configurable logic module' [patent_app_type] => 1 [patent_app_number] => 8/369208 [patent_app_country] => US [patent_app_date] => 1995-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1422 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502402.pdf [firstpage_image] =>[orig_patent_app_number] => 369208 [rel_patent_id] =>[rel_patent_doc_number] =>)