Search

David R. Hudspeth

Supervisory Patent Examiner (ID: 19114, Phone: (571)272-7843 , Office: P/2657 )

Most Active Art Unit
2504
Art Unit(s)
2651, 2509, 2641, 2657, 2504, 2626, 2681, 2741
Total Applications
1592
Issued Applications
1465
Pending Applications
21
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3512512 [patent_doc_number] => 05570042 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-29 [patent_title] => 'PECL input buffer' [patent_app_type] => 1 [patent_app_number] => 8/368106 [patent_app_country] => US [patent_app_date] => 1995-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2105 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/570/05570042.pdf [firstpage_image] =>[orig_patent_app_number] => 368106 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/368106
PECL input buffer Jan 2, 1995 Issued
Array ( [id] => 3485573 [patent_doc_number] => 05457405 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-10 [patent_title] => 'Complementary logic recovered energy circuit' [patent_app_type] => 1 [patent_app_number] => 8/364912 [patent_app_country] => US [patent_app_date] => 1994-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1919 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/457/05457405.pdf [firstpage_image] =>[orig_patent_app_number] => 364912 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/364912
Complementary logic recovered energy circuit Dec 26, 1994 Issued
Array ( [id] => 3525643 [patent_doc_number] => 05530381 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Integrated high-speed bipolar logic circuit method' [patent_app_type] => 1 [patent_app_number] => 8/359507 [patent_app_country] => US [patent_app_date] => 1994-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3385 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530381.pdf [firstpage_image] =>[orig_patent_app_number] => 359507 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/359507
Integrated high-speed bipolar logic circuit method Dec 19, 1994 Issued
Array ( [id] => 3535710 [patent_doc_number] => 05583455 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Semiconductor logic circuit using a first power source and a second power source' [patent_app_type] => 1 [patent_app_number] => 8/357517 [patent_app_country] => US [patent_app_date] => 1994-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 5881 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/583/05583455.pdf [firstpage_image] =>[orig_patent_app_number] => 357517 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/357517
Semiconductor logic circuit using a first power source and a second power source Dec 15, 1994 Issued
Array ( [id] => 3617820 [patent_doc_number] => 05534794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Selectable logic output stage' [patent_app_type] => 1 [patent_app_number] => 8/347710 [patent_app_country] => US [patent_app_date] => 1994-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3229 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/534/05534794.pdf [firstpage_image] =>[orig_patent_app_number] => 347710 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/347710
Selectable logic output stage Nov 30, 1994 Issued
Array ( [id] => 3557919 [patent_doc_number] => 05493234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-20 [patent_title] => 'Voltage down converter for semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/348992 [patent_app_country] => US [patent_app_date] => 1994-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3086 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/493/05493234.pdf [firstpage_image] =>[orig_patent_app_number] => 348992 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/348992
Voltage down converter for semiconductor memory device Nov 28, 1994 Issued
Array ( [id] => 3510576 [patent_doc_number] => 05514979 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'Methods and apparatus for dynamically reducing ringing of driver output signal' [patent_app_type] => 1 [patent_app_number] => 8/345307 [patent_app_country] => US [patent_app_date] => 1994-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 2224 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/514/05514979.pdf [firstpage_image] =>[orig_patent_app_number] => 345307 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/345307
Methods and apparatus for dynamically reducing ringing of driver output signal Nov 27, 1994 Issued
Array ( [id] => 3485624 [patent_doc_number] => 05457408 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-10 [patent_title] => 'Method and apparatus for verifying whether a bitstream received by a field programmable gate array (FPGA) is intended for that FPGA' [patent_app_type] => 1 [patent_app_number] => 8/344802 [patent_app_country] => US [patent_app_date] => 1994-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4606 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/457/05457408.pdf [firstpage_image] =>[orig_patent_app_number] => 344802 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/344802
Method and apparatus for verifying whether a bitstream received by a field programmable gate array (FPGA) is intended for that FPGA Nov 22, 1994 Issued
Array ( [id] => 3569550 [patent_doc_number] => 05483180 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-09 [patent_title] => 'Data and clock recovery circuit' [patent_app_type] => 1 [patent_app_number] => 8/346206 [patent_app_country] => US [patent_app_date] => 1994-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3123 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/483/05483180.pdf [firstpage_image] =>[orig_patent_app_number] => 346206 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/346206
Data and clock recovery circuit Nov 21, 1994 Issued
Array ( [id] => 3424503 [patent_doc_number] => 05479113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'User-configurable logic circuits comprising antifuses and multiplexer-based logic modules' [patent_app_type] => 1 [patent_app_number] => 8/342735 [patent_app_country] => US [patent_app_date] => 1994-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 4789 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/479/05479113.pdf [firstpage_image] =>[orig_patent_app_number] => 342735 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/342735
User-configurable logic circuits comprising antifuses and multiplexer-based logic modules Nov 20, 1994 Issued
08/342710 RECONFIGURABLE PROGRAMMABLE INTERCONNECT ARCHITECTURE Nov 20, 1994 Abandoned
Array ( [id] => 3700777 [patent_doc_number] => 05596284 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'System for, and method of, minimizing noise in an integrated circuit chip' [patent_app_type] => 1 [patent_app_number] => 8/338012 [patent_app_country] => US [patent_app_date] => 1994-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4689 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596284.pdf [firstpage_image] =>[orig_patent_app_number] => 338012 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/338012
System for, and method of, minimizing noise in an integrated circuit chip Nov 9, 1994 Issued
Array ( [id] => 3562862 [patent_doc_number] => 05502405 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Method and apparatus for CML/EC to CMOS/TTL translators' [patent_app_type] => 1 [patent_app_number] => 8/335908 [patent_app_country] => US [patent_app_date] => 1994-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4557 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502405.pdf [firstpage_image] =>[orig_patent_app_number] => 335908 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/335908
Method and apparatus for CML/EC to CMOS/TTL translators Nov 7, 1994 Issued
Array ( [id] => 3488332 [patent_doc_number] => 05446400 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'GTL compatible BICMOS input stage' [patent_app_type] => 1 [patent_app_number] => 8/334906 [patent_app_country] => US [patent_app_date] => 1994-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4843 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446400.pdf [firstpage_image] =>[orig_patent_app_number] => 334906 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/334906
GTL compatible BICMOS input stage Nov 6, 1994 Issued
Array ( [id] => 3462860 [patent_doc_number] => 05473269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-05 [patent_title] => 'Adiabatic dynamic logic' [patent_app_type] => 1 [patent_app_number] => 8/334296 [patent_app_country] => US [patent_app_date] => 1994-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 8584 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/473/05473269.pdf [firstpage_image] =>[orig_patent_app_number] => 334296 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/334296
Adiabatic dynamic logic Nov 3, 1994 Issued
Array ( [id] => 3117152 [patent_doc_number] => 05465056 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-07 [patent_title] => 'Apparatus for programmable circuit and signal switching' [patent_app_type] => 1 [patent_app_number] => 8/333524 [patent_app_country] => US [patent_app_date] => 1994-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 9207 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/465/05465056.pdf [firstpage_image] =>[orig_patent_app_number] => 333524 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/333524
Apparatus for programmable circuit and signal switching Nov 1, 1994 Issued
Array ( [id] => 3539266 [patent_doc_number] => 05557217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-17 [patent_title] => 'High-density erasable programmable logic device architecture using multiplexer interconnections' [patent_app_type] => 1 [patent_app_number] => 8/331964 [patent_app_country] => US [patent_app_date] => 1994-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6601 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/557/05557217.pdf [firstpage_image] =>[orig_patent_app_number] => 331964 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/331964
High-density erasable programmable logic device architecture using multiplexer interconnections Oct 30, 1994 Issued
Array ( [id] => 3581120 [patent_doc_number] => 05523702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Sequentially switching output buffers' [patent_app_type] => 1 [patent_app_number] => 8/332408 [patent_app_country] => US [patent_app_date] => 1994-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 33 [patent_no_of_words] => 7525 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/523/05523702.pdf [firstpage_image] =>[orig_patent_app_number] => 332408 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/332408
Sequentially switching output buffers Oct 30, 1994 Issued
Array ( [id] => 3117134 [patent_doc_number] => 05465055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-07 [patent_title] => 'RAM-logic tile for field programmable gate arrays' [patent_app_type] => 1 [patent_app_number] => 8/325714 [patent_app_country] => US [patent_app_date] => 1994-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2534 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/465/05465055.pdf [firstpage_image] =>[orig_patent_app_number] => 325714 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/325714
RAM-logic tile for field programmable gate arrays Oct 18, 1994 Issued
Array ( [id] => 3510650 [patent_doc_number] => 05514984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'Active pull down type ECL apparatus capable of stable operation' [patent_app_type] => 1 [patent_app_number] => 8/324500 [patent_app_country] => US [patent_app_date] => 1994-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 2639 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/514/05514984.pdf [firstpage_image] =>[orig_patent_app_number] => 324500 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/324500
Active pull down type ECL apparatus capable of stable operation Oct 17, 1994 Issued
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