
David R. Hudspeth
Supervisory Patent Examiner (ID: 19114, Phone: (571)272-7843 , Office: P/2657 )
| Most Active Art Unit | 2504 |
| Art Unit(s) | 2651, 2509, 2641, 2657, 2504, 2626, 2681, 2741 |
| Total Applications | 1592 |
| Issued Applications | 1465 |
| Pending Applications | 21 |
| Abandoned Applications | 105 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3122384
[patent_doc_number] => 05450022
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-09-12
[patent_title] => 'Structure and method for configuration of a field programmable gate array'
[patent_app_type] => 1
[patent_app_number] => 8/319756
[patent_app_country] => US
[patent_app_date] => 1994-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3238
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/450/05450022.pdf
[firstpage_image] =>[orig_patent_app_number] => 319756
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/319756 | Structure and method for configuration of a field programmable gate array | Oct 6, 1994 | Issued |
Array
(
[id] => 3519056
[patent_doc_number] => 05512847
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-30
[patent_title] => 'BiCMOS tri-state output driver'
[patent_app_type] => 1
[patent_app_number] => 8/321012
[patent_app_country] => US
[patent_app_date] => 1994-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 40
[patent_no_of_words] => 18149
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/512/05512847.pdf
[firstpage_image] =>[orig_patent_app_number] => 321012
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/321012 | BiCMOS tri-state output driver | Oct 5, 1994 | Issued |
Array
(
[id] => 3673483
[patent_doc_number] => 05600268
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-04
[patent_title] => 'Gate circuit of combined field-effect and bipolar transistors'
[patent_app_type] => 1
[patent_app_number] => 8/315594
[patent_app_country] => US
[patent_app_date] => 1994-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 17
[patent_no_of_words] => 5972
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/600/05600268.pdf
[firstpage_image] =>[orig_patent_app_number] => 315594
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/315594 | Gate circuit of combined field-effect and bipolar transistors | Sep 29, 1994 | Issued |
Array
(
[id] => 3521319
[patent_doc_number] => 05486776
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-23
[patent_title] => 'Antifuse-based programmable logic circuit'
[patent_app_type] => 1
[patent_app_number] => 8/315009
[patent_app_country] => US
[patent_app_date] => 1994-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 1981
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/486/05486776.pdf
[firstpage_image] =>[orig_patent_app_number] => 315009
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/315009 | Antifuse-based programmable logic circuit | Sep 28, 1994 | Issued |
Array
(
[id] => 3554693
[patent_doc_number] => 05548228
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-20
[patent_title] => 'Reconfigurable programmable logic device having static and non-volatile memory'
[patent_app_type] => 1
[patent_app_number] => 8/314012
[patent_app_country] => US
[patent_app_date] => 1994-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5172
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/548/05548228.pdf
[firstpage_image] =>[orig_patent_app_number] => 314012
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/314012 | Reconfigurable programmable logic device having static and non-volatile memory | Sep 27, 1994 | Issued |
Array
(
[id] => 3522822
[patent_doc_number] => 05506518
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-09
[patent_title] => 'Antifuse-based programmable logic circuit'
[patent_app_type] => 1
[patent_app_number] => 8/310114
[patent_app_country] => US
[patent_app_date] => 1994-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2003
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/506/05506518.pdf
[firstpage_image] =>[orig_patent_app_number] => 310114
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/310114 | Antifuse-based programmable logic circuit | Sep 19, 1994 | Issued |
Array
(
[id] => 3530711
[patent_doc_number] => 05528177
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-18
[patent_title] => 'Complementary field-effect transistor logic circuits for wave pipelining'
[patent_app_type] => 1
[patent_app_number] => 8/307932
[patent_app_country] => US
[patent_app_date] => 1994-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 32
[patent_no_of_words] => 12272
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/528/05528177.pdf
[firstpage_image] =>[orig_patent_app_number] => 307932
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/307932 | Complementary field-effect transistor logic circuits for wave pipelining | Sep 15, 1994 | Issued |
Array
(
[id] => 3584806
[patent_doc_number] => 05491429
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-13
[patent_title] => 'Apparatus for reducing current consumption in a CMOS inverter circuit'
[patent_app_type] => 1
[patent_app_number] => 8/307111
[patent_app_country] => US
[patent_app_date] => 1994-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 1998
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/491/05491429.pdf
[firstpage_image] =>[orig_patent_app_number] => 307111
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/307111 | Apparatus for reducing current consumption in a CMOS inverter circuit | Sep 15, 1994 | Issued |
Array
(
[id] => 3464956
[patent_doc_number] => 05442305
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-15
[patent_title] => 'Active bus termination device'
[patent_app_type] => 1
[patent_app_number] => 8/306010
[patent_app_country] => US
[patent_app_date] => 1994-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 19
[patent_no_of_words] => 12856
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/442/05442305.pdf
[firstpage_image] =>[orig_patent_app_number] => 306010
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/306010 | Active bus termination device | Sep 13, 1994 | Issued |
Array
(
[id] => 3464971
[patent_doc_number] => 05442306
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-15
[patent_title] => 'Field programmable gate array using look-up tables, multiplexers and decoders'
[patent_app_type] => 1
[patent_app_number] => 8/304013
[patent_app_country] => US
[patent_app_date] => 1994-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 3474
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/442/05442306.pdf
[firstpage_image] =>[orig_patent_app_number] => 304013
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/304013 | Field programmable gate array using look-up tables, multiplexers and decoders | Sep 8, 1994 | Issued |
Array
(
[id] => 3494708
[patent_doc_number] => 05471149
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-28
[patent_title] => 'High-speed large output amplitude voltage level shifting circuit'
[patent_app_type] => 1
[patent_app_number] => 8/300220
[patent_app_country] => US
[patent_app_date] => 1994-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 19
[patent_no_of_words] => 3640
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/471/05471149.pdf
[firstpage_image] =>[orig_patent_app_number] => 300220
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/300220 | High-speed large output amplitude voltage level shifting circuit | Sep 5, 1994 | Issued |
Array
(
[id] => 3597723
[patent_doc_number] => 05521530
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-28
[patent_title] => 'Efficient method and resulting structure for integrated circuits with flexible I/O interface and power supply voltages'
[patent_app_type] => 1
[patent_app_number] => 8/299004
[patent_app_country] => US
[patent_app_date] => 1994-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 10444
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/521/05521530.pdf
[firstpage_image] =>[orig_patent_app_number] => 299004
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/299004 | Efficient method and resulting structure for integrated circuits with flexible I/O interface and power supply voltages | Aug 30, 1994 | Issued |
Array
(
[id] => 3495564
[patent_doc_number] => 05440243
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-08
[patent_title] => 'Apparatus and method for allowing a dynamic logic gate to operation statically using subthreshold conduction precharging'
[patent_app_type] => 1
[patent_app_number] => 8/295157
[patent_app_country] => US
[patent_app_date] => 1994-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 33
[patent_no_of_words] => 13331
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/440/05440243.pdf
[firstpage_image] =>[orig_patent_app_number] => 295157
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/295157 | Apparatus and method for allowing a dynamic logic gate to operation statically using subthreshold conduction precharging | Aug 23, 1994 | Issued |
Array
(
[id] => 3453769
[patent_doc_number] => 05430830
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-07-04
[patent_title] => 'Adaptive weight adjusting circuit for an neural network'
[patent_app_type] => 1
[patent_app_number] => 8/293631
[patent_app_country] => US
[patent_app_date] => 1994-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3949
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 251
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/430/05430830.pdf
[firstpage_image] =>[orig_patent_app_number] => 293631
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/293631 | Adaptive weight adjusting circuit for an neural network | Aug 21, 1994 | Issued |
Array
(
[id] => 3122438
[patent_doc_number] => 05450025
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-09-12
[patent_title] => 'Tristate driver for interfacing to a bus subject to overvoltage conditions'
[patent_app_type] => 1
[patent_app_number] => 8/290439
[patent_app_country] => US
[patent_app_date] => 1994-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 6068
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 13
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/450/05450025.pdf
[firstpage_image] =>[orig_patent_app_number] => 290439
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/290439 | Tristate driver for interfacing to a bus subject to overvoltage conditions | Aug 14, 1994 | Issued |
Array
(
[id] => 3414236
[patent_doc_number] => 05438283
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-01
[patent_title] => 'Fast static cascode logic gate'
[patent_app_type] => 1
[patent_app_number] => 8/288918
[patent_app_country] => US
[patent_app_date] => 1994-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3573
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/438/05438283.pdf
[firstpage_image] =>[orig_patent_app_number] => 288918
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/288918 | Fast static cascode logic gate | Aug 10, 1994 | Issued |
Array
(
[id] => 3543091
[patent_doc_number] => 05495186
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-27
[patent_title] => 'Differential type MOS transmission circuit'
[patent_app_type] => 1
[patent_app_number] => 8/275008
[patent_app_country] => US
[patent_app_date] => 1994-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 11811
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 316
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/495/05495186.pdf
[firstpage_image] =>[orig_patent_app_number] => 275008
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/275008 | Differential type MOS transmission circuit | Jul 12, 1994 | Issued |
Array
(
[id] => 3485609
[patent_doc_number] => 05457407
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-10
[patent_title] => 'Binary weighted reference circuit for a variable impedance output buffer'
[patent_app_type] => 1
[patent_app_number] => 8/268118
[patent_app_country] => US
[patent_app_date] => 1994-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2511
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/457/05457407.pdf
[firstpage_image] =>[orig_patent_app_number] => 268118
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/268118 | Binary weighted reference circuit for a variable impedance output buffer | Jul 5, 1994 | Issued |
Array
(
[id] => 3594385
[patent_doc_number] => 05497105
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-05
[patent_title] => 'Programmable output pad with circuitry for reducing ground bounce noise and power supply noise and method therefor'
[patent_app_type] => 1
[patent_app_number] => 8/269800
[patent_app_country] => US
[patent_app_date] => 1994-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 7205
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/497/05497105.pdf
[firstpage_image] =>[orig_patent_app_number] => 269800
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/269800 | Programmable output pad with circuitry for reducing ground bounce noise and power supply noise and method therefor | Jun 29, 1994 | Issued |
| 08/269794 | METHOD AND APPARATUS FOR PROGRAMMABLE CIRCUIT AND SIGNAL SWITCHING | Jun 29, 1994 | Abandoned |