David R. Hudspeth

Array ( [id] => 3454318 [patent_doc_number] => 05424657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-13 [patent_title] => 'Method and apparatus for implementing a common mode level shift in a bus transceiver incorporating a high speed binary data transfer mode with a ternary control transfer mode' [patent_app_type] => 1 [patent_app_number] => 8/221029 [patent_app_country] => US [patent_app_date] => 1994-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5998 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/424/05424657.pdf [firstpage_image] =>[orig_patent_app_number] => 221029 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3448427 [patent_doc_number] => 05398000 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-14 [patent_title] => 'Simple and high speed BICMOS tristate buffer circuit' [patent_app_type] => 1 [patent_app_number] => 8/220114 [patent_app_country] => US [patent_app_date] => 1994-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3954 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/398/05398000.pdf [firstpage_image] =>[orig_patent_app_number] => 220114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3495608 [patent_doc_number] => 05440246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'Programmable circuit with fusible latch' [patent_app_type] => 1 [patent_app_number] => 8/216208 [patent_app_country] => US [patent_app_date] => 1994-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1355 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/440/05440246.pdf [firstpage_image] =>[orig_patent_app_number] => 216208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3431160 [patent_doc_number] => 05416431 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-16 [patent_title] => 'Integrated circuit clock driver having improved layout' [patent_app_type] => 1 [patent_app_number] => 8/216203 [patent_app_country] => US [patent_app_date] => 1994-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3874 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/416/05416431.pdf [firstpage_image] =>[orig_patent_app_number] => 216203 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3464929 [patent_doc_number] => 05442303 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-15 [patent_title] => 'Electromagnetically coupled fail-safe logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/204405 [patent_app_country] => US [patent_app_date] => 1994-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 8764 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/442/05442303.pdf [firstpage_image] =>[orig_patent_app_number] => 204405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3491668 [patent_doc_number] => 05426377 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-20 [patent_title] => 'BiMIS circuit' [patent_app_type] => 1 [patent_app_number] => 8/208827 [patent_app_country] => US [patent_app_date] => 1994-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8090 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/426/05426377.pdf [firstpage_image] =>[orig_patent_app_number] => 208827 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3111933 [patent_doc_number] => 05418475 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-23 [patent_title] => 'Input/output circuit having the input buffer circuit being connected in parallel with two transistors with the same polarity' [patent_app_type] => 1 [patent_app_number] => 8/208111 [patent_app_country] => US [patent_app_date] => 1994-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4513 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/418/05418475.pdf [firstpage_image] =>[orig_patent_app_number] => 208111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3484385 [patent_doc_number] => 05399924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-21 [patent_title] => 'Low current optional inverter' [patent_app_type] => 1 [patent_app_number] => 8/204939 [patent_app_country] => US [patent_app_date] => 1994-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3000 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/399/05399924.pdf [firstpage_image] =>[orig_patent_app_number] => 204939 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3098352 [patent_doc_number] => 05369314 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-29 [patent_title] => 'Programmable logic device with redundant circuitry' [patent_app_type] => 1 [patent_app_number] => 8/199620 [patent_app_country] => US [patent_app_date] => 1994-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6329 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/369/05369314.pdf [firstpage_image] =>[orig_patent_app_number] => 199620 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3495631 [patent_doc_number] => 05440248 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'Power-saver differential input buffer' [patent_app_type] => 1 [patent_app_number] => 8/189222 [patent_app_country] => US [patent_app_date] => 1994-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2052 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/440/05440248.pdf [firstpage_image] =>[orig_patent_app_number] => 189222 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3466467 [patent_doc_number] => 05391943 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Gate array cell with predefined connection patterns' [patent_app_type] => 1 [patent_app_number] => 8/178712 [patent_app_country] => US [patent_app_date] => 1994-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2286 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/391/05391943.pdf [firstpage_image] =>[orig_patent_app_number] => 178712 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3421319 [patent_doc_number] => 05453707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-26 [patent_title] => 'Polyphase clock generation circuit' [patent_app_type] => 1 [patent_app_number] => 8/178026 [patent_app_country] => US [patent_app_date] => 1994-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12306 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/453/05453707.pdf [firstpage_image] =>[orig_patent_app_number] => 178026 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3112869 [patent_doc_number] => 05408144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-18 [patent_title] => 'Semiconductor integrated circuits with power reduction mechanism' [patent_app_type] => 1 [patent_app_number] => 8/178020 [patent_app_country] => US [patent_app_date] => 1994-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 15376 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/408/05408144.pdf [firstpage_image] =>[orig_patent_app_number] => 178020 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3429053 [patent_doc_number] => 05422582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-06 [patent_title] => 'Diode coupled CMOS logic design for quasi-static resistive dissipation with multi-output capability' [patent_app_type] => 1 [patent_app_number] => 8/175709 [patent_app_country] => US [patent_app_date] => 1993-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 1676 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/422/05422582.pdf [firstpage_image] =>[orig_patent_app_number] => 175709 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3484417 [patent_doc_number] => 05399926 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-21 [patent_title] => 'Connected processing systems including mutual power off and signal path disconnect detection' [patent_app_type] => 1 [patent_app_number] => 8/175914 [patent_app_country] => US [patent_app_date] => 1993-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4686 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 430 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/399/05399926.pdf [firstpage_image] =>[orig_patent_app_number] => 175914 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3485897 [patent_doc_number] => 05406143 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-11 [patent_title] => 'GTL to CMOS level signal converter, method and apparatus' [patent_app_type] => 1 [patent_app_number] => 8/172023 [patent_app_country] => US [patent_app_date] => 1993-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4120 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/406/05406143.pdf [firstpage_image] =>[orig_patent_app_number] => 172023 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3484343 [patent_doc_number] => 05399921 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-21 [patent_title] => 'Dynamic complementary pass-transistor logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/166625 [patent_app_country] => US [patent_app_date] => 1993-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 14059 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 500 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/399/05399921.pdf [firstpage_image] =>[orig_patent_app_number] => 166625 [rel_patent_id] =>[rel_patent_doc_number] =>)