Search

David R. Hudspeth

Supervisory Patent Examiner (ID: 19114, Phone: (571)272-7843 , Office: P/2657 )

Most Active Art Unit
2504
Art Unit(s)
2651, 2509, 2641, 2657, 2504, 2626, 2681, 2741
Total Applications
1592
Issued Applications
1465
Pending Applications
21
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3062172 [patent_doc_number] => 05338983 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-16 [patent_title] => 'Application specific exclusive of based logic module architecture for FPGAs' [patent_app_type] => 1 [patent_app_number] => 8/166330 [patent_app_country] => US [patent_app_date] => 1993-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2230 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/338/05338983.pdf [firstpage_image] =>[orig_patent_app_number] => 166330 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/166330
Application specific exclusive of based logic module architecture for FPGAs Dec 9, 1993 Issued
08/150927 SELECTIVE CURRENT LIMITS IN SEMICONDUCTOR DEVICES Nov 11, 1993 Abandoned
Array ( [id] => 3465966 [patent_doc_number] => 05469003 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-21 [patent_title] => 'Hierarchically connectable configurable cellular array' [patent_app_type] => 1 [patent_app_number] => 8/148793 [patent_app_country] => US [patent_app_date] => 1993-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 61 [patent_no_of_words] => 27747 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/469/05469003.pdf [firstpage_image] =>[orig_patent_app_number] => 148793 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/148793
Hierarchically connectable configurable cellular array Nov 4, 1993 Issued
Array ( [id] => 3494646 [patent_doc_number] => 05440182 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'Dynamic logic interconnect speed-up circuit' [patent_app_type] => 1 [patent_app_number] => 8/142900 [patent_app_country] => US [patent_app_date] => 1993-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 9831 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/440/05440182.pdf [firstpage_image] =>[orig_patent_app_number] => 142900 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/142900
Dynamic logic interconnect speed-up circuit Oct 21, 1993 Issued
Array ( [id] => 3433190 [patent_doc_number] => 05455521 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-03 [patent_title] => 'Self-timed interconnect speed-up circuit' [patent_app_type] => 1 [patent_app_number] => 8/142901 [patent_app_country] => US [patent_app_date] => 1993-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 10006 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/455/05455521.pdf [firstpage_image] =>[orig_patent_app_number] => 142901 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/142901
Self-timed interconnect speed-up circuit Oct 21, 1993 Issued
Array ( [id] => 3466416 [patent_doc_number] => 05391940 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Pad driver circuit with powered down device protection' [patent_app_type] => 1 [patent_app_number] => 8/140347 [patent_app_country] => US [patent_app_date] => 1993-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2238 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/391/05391940.pdf [firstpage_image] =>[orig_patent_app_number] => 140347 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/140347
Pad driver circuit with powered down device protection Oct 19, 1993 Issued
Array ( [id] => 3481517 [patent_doc_number] => 05432463 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-11 [patent_title] => 'High speed NOR gate with small output voltage swings' [patent_app_type] => 1 [patent_app_number] => 8/138303 [patent_app_country] => US [patent_app_date] => 1993-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4032 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/432/05432463.pdf [firstpage_image] =>[orig_patent_app_number] => 138303 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/138303
High speed NOR gate with small output voltage swings Oct 14, 1993 Issued
08/138819 FIELD PROGRAMMABLE ANTIFUSE DEVICE AND PROGRAMMING METHOD THEREFOR Oct 14, 1993 Abandoned
Array ( [id] => 3052256 [patent_doc_number] => 05304860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-19 [patent_title] => 'Method for powering down a microprocessor embedded within a gate array' [patent_app_type] => 1 [patent_app_number] => 8/135637 [patent_app_country] => US [patent_app_date] => 1993-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 8505 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/304/05304860.pdf [firstpage_image] =>[orig_patent_app_number] => 135637 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/135637
Method for powering down a microprocessor embedded within a gate array Oct 11, 1993 Issued
Array ( [id] => 3492706 [patent_doc_number] => 05475322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'Clock frequency multiplying and squaring circuit and method' [patent_app_type] => 1 [patent_app_number] => 8/135113 [patent_app_country] => US [patent_app_date] => 1993-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2213 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/475/05475322.pdf [firstpage_image] =>[orig_patent_app_number] => 135113 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/135113
Clock frequency multiplying and squaring circuit and method Oct 11, 1993 Issued
Array ( [id] => 3431517 [patent_doc_number] => 05404057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Output circuit for outputting signals having different logical amplitudes' [patent_app_type] => 1 [patent_app_number] => 8/134021 [patent_app_country] => US [patent_app_date] => 1993-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4957 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404057.pdf [firstpage_image] =>[orig_patent_app_number] => 134021 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/134021
Output circuit for outputting signals having different logical amplitudes Oct 7, 1993 Issued
Array ( [id] => 3450499 [patent_doc_number] => 05387823 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Fuse-programmable redundancy control circuit' [patent_app_type] => 1 [patent_app_number] => 8/132111 [patent_app_country] => US [patent_app_date] => 1993-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3000 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/387/05387823.pdf [firstpage_image] =>[orig_patent_app_number] => 132111 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/132111
Fuse-programmable redundancy control circuit Oct 4, 1993 Issued
Array ( [id] => 3118514 [patent_doc_number] => 05396124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'Circuit redundancy having a variable impedance circuit' [patent_app_type] => 1 [patent_app_number] => 8/128726 [patent_app_country] => US [patent_app_date] => 1993-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 9862 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/396/05396124.pdf [firstpage_image] =>[orig_patent_app_number] => 128726 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/128726
Circuit redundancy having a variable impedance circuit Sep 29, 1993 Issued
Array ( [id] => 3464085 [patent_doc_number] => 05442246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-15 [patent_title] => 'Programmable logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/128223 [patent_app_country] => US [patent_app_date] => 1993-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 116 [patent_figures_cnt] => 190 [patent_no_of_words] => 49137 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/442/05442246.pdf [firstpage_image] =>[orig_patent_app_number] => 128223 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/128223
Programmable logic circuit Sep 28, 1993 Issued
Array ( [id] => 3038475 [patent_doc_number] => 05329176 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-12 [patent_title] => 'Self-timed clocking system and method for self-timed dynamic logic circuits' [patent_app_type] => 1 [patent_app_number] => 8/137902 [patent_app_country] => US [patent_app_date] => 1993-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7679 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/329/05329176.pdf [firstpage_image] =>[orig_patent_app_number] => 137902 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/137902
Self-timed clocking system and method for self-timed dynamic logic circuits Sep 28, 1993 Issued
Array ( [id] => 3447141 [patent_doc_number] => 05430389 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Output circuit with a current injection circuit including a reference voltage generator' [patent_app_type] => 1 [patent_app_number] => 8/127611 [patent_app_country] => US [patent_app_date] => 1993-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 17699 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/430/05430389.pdf [firstpage_image] =>[orig_patent_app_number] => 127611 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/127611
Output circuit with a current injection circuit including a reference voltage generator Sep 27, 1993 Issued
Array ( [id] => 3111912 [patent_doc_number] => 05418474 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-23 [patent_title] => 'Circuit for reducing transient simultaneous conduction' [patent_app_type] => 1 [patent_app_number] => 8/126914 [patent_app_country] => US [patent_app_date] => 1993-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4784 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/418/05418474.pdf [firstpage_image] =>[orig_patent_app_number] => 126914 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/126914
Circuit for reducing transient simultaneous conduction Sep 23, 1993 Issued
08/124820 APPARATUS AND METHOD FOR ALLOWING A DYNAMIC LOGIC GATE TO OPERATE STATICALLY USING SUBTHRESHOLD CONDUCTION PRECHARGING Sep 20, 1993 Abandoned
Array ( [id] => 3126329 [patent_doc_number] => 05384499 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-24 [patent_title] => 'High-density erasable programmable logic device architecture using multiplexer interconnections' [patent_app_type] => 1 [patent_app_number] => 8/123435 [patent_app_country] => US [patent_app_date] => 1993-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 7503 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/384/05384499.pdf [firstpage_image] =>[orig_patent_app_number] => 123435 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/123435
High-density erasable programmable logic device architecture using multiplexer interconnections Sep 16, 1993 Issued
Array ( [id] => 3124636 [patent_doc_number] => 05381056 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-10 [patent_title] => 'CMOS buffer having output terminal overvoltage-caused latch-up protection' [patent_app_type] => 1 [patent_app_number] => 8/121725 [patent_app_country] => US [patent_app_date] => 1993-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1537 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/381/05381056.pdf [firstpage_image] =>[orig_patent_app_number] => 121725 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/121725
CMOS buffer having output terminal overvoltage-caused latch-up protection Sep 14, 1993 Issued
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