| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
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[patent_doc_number] => 05455520
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-03
[patent_title] => 'CMOS input circuit for providing logical output signal from TTL compatible input signal'
[patent_app_type] => 1
[patent_app_number] => 8/121326
[patent_app_country] => US
[patent_app_date] => 1993-09-14
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[pdf_file] => patents/05/455/05455520.pdf
[firstpage_image] =>[orig_patent_app_number] => 121326
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/121326 | CMOS input circuit for providing logical output signal from TTL compatible input signal | Sep 13, 1993 | Issued |
Array
(
[id] => 3118581
[patent_doc_number] => 05396128
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-07
[patent_title] => 'Output circuit for interfacing integrated circuits having different power supply potentials'
[patent_app_type] => 1
[patent_app_number] => 8/120506
[patent_app_country] => US
[patent_app_date] => 1993-09-13
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[firstpage_image] =>[orig_patent_app_number] => 120506
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/120506 | Output circuit for interfacing integrated circuits having different power supply potentials | Sep 12, 1993 | Issued |
Array
(
[id] => 3009864
[patent_doc_number] => 05374861
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-20
[patent_title] => 'Differential termination network for differential transmitters and receivers'
[patent_app_type] => 1
[patent_app_number] => 8/118920
[patent_app_country] => US
[patent_app_date] => 1993-09-10
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/374/05374861.pdf
[firstpage_image] =>[orig_patent_app_number] => 118920
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/118920 | Differential termination network for differential transmitters and receivers | Sep 9, 1993 | Issued |
Array
(
[id] => 3485558
[patent_doc_number] => 05457404
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-10
[patent_title] => 'Zero-power OR gate'
[patent_app_type] => 1
[patent_app_number] => 8/118801
[patent_app_country] => US
[patent_app_date] => 1993-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/05/457/05457404.pdf
[firstpage_image] =>[orig_patent_app_number] => 118801
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/118801 | Zero-power OR gate | Sep 7, 1993 | Issued |
Array
(
[id] => 3112923
[patent_doc_number] => 05408147
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-18
[patent_title] => 'VCC translator circuit'
[patent_app_type] => 1
[patent_app_number] => 8/116920
[patent_app_country] => US
[patent_app_date] => 1993-09-07
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[pdf_file] => patents/05/408/05408147.pdf
[firstpage_image] =>[orig_patent_app_number] => 116920
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/116920 | VCC translator circuit | Sep 6, 1993 | Issued |
Array
(
[id] => 3130232
[patent_doc_number] => 05436579
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-07-25
[patent_title] => 'Input transition detection circuit for zero-power part'
[patent_app_type] => 1
[patent_app_number] => 8/118123
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[firstpage_image] =>[orig_patent_app_number] => 118123
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/118123 | Input transition detection circuit for zero-power part | Sep 6, 1993 | Issued |
Array
(
[id] => 3420636
[patent_doc_number] => 05394033
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-28
[patent_title] => 'Structure and method for implementing hierarchical routing pools in a programmable logic circuit'
[patent_app_type] => 1
[patent_app_number] => 8/115723
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[pdf_file] => patents/05/394/05394033.pdf
[firstpage_image] =>[orig_patent_app_number] => 115723
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/115723 | Structure and method for implementing hierarchical routing pools in a programmable logic circuit | Aug 31, 1993 | Issued |
Array
(
[id] => 3041445
[patent_doc_number] => 05373204
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-13
[patent_title] => 'Self-timed clocking transfer control circuit'
[patent_app_type] => 1
[patent_app_number] => 8/113824
[patent_app_country] => US
[patent_app_date] => 1993-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/05/373/05373204.pdf
[firstpage_image] =>[orig_patent_app_number] => 113824
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/113824 | Self-timed clocking transfer control circuit | Aug 30, 1993 | Issued |
| 08/111506 | GATE CIRCUIT OF COMBINED FIELD-EFFECT AND BIPOLAR TRANSISTORS | Aug 23, 1993 | Abandoned |
Array
(
[id] => 3130103
[patent_doc_number] => 05436572
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-07-25
[patent_title] => 'Semiconductor integrated circuuit device of dual configuration having enhanced soft error withstanding capacity'
[patent_app_type] => 1
[patent_app_number] => 8/109518
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[firstpage_image] =>[orig_patent_app_number] => 109518
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/109518 | Semiconductor integrated circuuit device of dual configuration having enhanced soft error withstanding capacity | Aug 19, 1993 | Issued |
Array
(
[id] => 3416353
[patent_doc_number] => 05412260
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-02
[patent_title] => 'Multiplexed control pins for in-system programming and boundary scan state machines in a high density programmable logic device'
[patent_app_type] => 1
[patent_app_number] => 8/106263
[patent_app_country] => US
[patent_app_date] => 1993-08-13
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[pdf_file] => patents/05/412/05412260.pdf
[firstpage_image] =>[orig_patent_app_number] => 106263
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/106263 | Multiplexed control pins for in-system programming and boundary scan state machines in a high density programmable logic device | Aug 12, 1993 | Issued |
Array
(
[id] => 3076321
[patent_doc_number] => 05336951
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-09
[patent_title] => 'Structure and method for multiplexing pins for in-system programming'
[patent_app_type] => 1
[patent_app_number] => 8/106498
[patent_app_country] => US
[patent_app_date] => 1993-08-13
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[pdf_file] => patents/05/336/05336951.pdf
[firstpage_image] =>[orig_patent_app_number] => 106498
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/106498 | Structure and method for multiplexing pins for in-system programming | Aug 12, 1993 | Issued |
Array
(
[id] => 3034790
[patent_doc_number] => 05343090
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-30
[patent_title] => 'Speed enhancement technique for CMOS circuits'
[patent_app_type] => 1
[patent_app_number] => 8/105768
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[patent_app_date] => 1993-08-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/105768 | Speed enhancement technique for CMOS circuits | Aug 10, 1993 | Issued |
Array
(
[id] => 3119684
[patent_doc_number] => 05410194
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[patent_kind] => NA
[patent_issue_date] => 1995-04-25
[patent_title] => 'Asynchronous or synchronous load multifunction flip-flop'
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[firstpage_image] =>[orig_patent_app_number] => 105827
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/105827 | Asynchronous or synchronous load multifunction flip-flop | Aug 10, 1993 | Issued |
Array
(
[id] => 3458425
[patent_doc_number] => 05378940
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-03
[patent_title] => 'Charge recovery logic including split level logic'
[patent_app_type] => 1
[patent_app_number] => 8/102477
[patent_app_country] => US
[patent_app_date] => 1993-08-03
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[pdf_file] => patents/05/378/05378940.pdf
[firstpage_image] =>[orig_patent_app_number] => 102477
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/102477 | Charge recovery logic including split level logic | Aug 2, 1993 | Issued |
| 08/094028 | METHOD OF TRANSMITTING DIGITIZED, BLOCK CODED AUDIO SIGNALS USING SCALE FACTORS | Jul 25, 1993 | Pending |
Array
(
[id] => 3466453
[patent_doc_number] => 05391942
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[patent_kind] => NA
[patent_issue_date] => 1995-02-21
[patent_title] => 'Clock distribution scheme for user-programmable logic array architecture'
[patent_app_type] => 1
[patent_app_number] => 8/095264
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[pdf_file] => patents/05/391/05391942.pdf
[firstpage_image] =>[orig_patent_app_number] => 095264
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/095264 | Clock distribution scheme for user-programmable logic array architecture | Jul 20, 1993 | Issued |
Array
(
[id] => 3058481
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[patent_kind] => NA
[patent_issue_date] => 1994-09-06
[patent_title] => 'IIL circuit and integrated circuit having the same'
[patent_app_type] => 1
[patent_app_number] => 8/086202
[patent_app_country] => US
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[pdf_file] => patents/05/345/05345116.pdf
[firstpage_image] =>[orig_patent_app_number] => 086202
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/086202 | IIL circuit and integrated circuit having the same | Jul 5, 1993 | Issued |
Array
(
[id] => 3491056
[patent_doc_number] => 05426335
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-06-20
[patent_title] => 'Pinout architecture for a family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix'
[patent_app_type] => 1
[patent_app_number] => 8/085601
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/085601 | Pinout architecture for a family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix | Jun 29, 1993 | Issued |
| 08/084624 | BICMOS TRI-STATE OUTPUT DRIVER | Jun 29, 1993 | Pending |