Search

David R. Hudspeth

Supervisory Patent Examiner (ID: 19114, Phone: (571)272-7843 , Office: P/2657 )

Most Active Art Unit
2504
Art Unit(s)
2651, 2509, 2641, 2657, 2504, 2626, 2681, 2741
Total Applications
1592
Issued Applications
1465
Pending Applications
21
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3451271 [patent_doc_number] => 05420525 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'Low switching noise output buffer' [patent_app_type] => 1 [patent_app_number] => 8/084727 [patent_app_country] => US [patent_app_date] => 1993-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 10028 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/420/05420525.pdf [firstpage_image] =>[orig_patent_app_number] => 084727 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/084727
Low switching noise output buffer Jun 27, 1993 Issued
Array ( [id] => 3080387 [patent_doc_number] => 05296759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Diagonal wiring between abutting logic cells in a configurable logic array' [patent_app_type] => 1 [patent_app_number] => 8/079213 [patent_app_country] => US [patent_app_date] => 1993-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 44 [patent_no_of_words] => 11603 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/296/05296759.pdf [firstpage_image] =>[orig_patent_app_number] => 079213 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/079213
Diagonal wiring between abutting logic cells in a configurable logic array Jun 17, 1993 Issued
Array ( [id] => 3080723 [patent_doc_number] => 05323069 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-21 [patent_title] => 'Direct I/O access to express bussing in a configurable logic array' [patent_app_type] => 1 [patent_app_number] => 8/079161 [patent_app_country] => US [patent_app_date] => 1993-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 47 [patent_no_of_words] => 11506 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/323/05323069.pdf [firstpage_image] =>[orig_patent_app_number] => 079161 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/079161
Direct I/O access to express bussing in a configurable logic array Jun 17, 1993 Issued
Array ( [id] => 3091008 [patent_doc_number] => RE034916 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'Method and circuitry for testing a programmable logic device' [patent_app_type] => 2 [patent_app_number] => 8/076653 [patent_app_country] => US [patent_app_date] => 1993-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5565 [patent_no_of_claims] => 78 [patent_no_of_ind_claims] => 41 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/034/RE034916.pdf [firstpage_image] =>[orig_patent_app_number] => 076653 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/076653
Method and circuitry for testing a programmable logic device Jun 10, 1993 Issued
Array ( [id] => 3450542 [patent_doc_number] => 05387826 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Overvoltage protection against charge leakage in an output driver' [patent_app_type] => 1 [patent_app_number] => 8/072899 [patent_app_country] => US [patent_app_date] => 1993-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2109 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/387/05387826.pdf [firstpage_image] =>[orig_patent_app_number] => 072899 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/072899
Overvoltage protection against charge leakage in an output driver Jun 6, 1993 Issued
Array ( [id] => 3112021 [patent_doc_number] => 05418480 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-23 [patent_title] => 'Logic cell using only two N type transistors for generating each logic function' [patent_app_type] => 1 [patent_app_number] => 8/068200 [patent_app_country] => US [patent_app_date] => 1993-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2184 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/418/05418480.pdf [firstpage_image] =>[orig_patent_app_number] => 068200 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/068200
Logic cell using only two N type transistors for generating each logic function May 27, 1993 Issued
Array ( [id] => 3428488 [patent_doc_number] => 05459414 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Adiabatic dynamic logic' [patent_app_type] => 1 [patent_app_number] => 8/069926 [patent_app_country] => US [patent_app_date] => 1993-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 8586 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459414.pdf [firstpage_image] =>[orig_patent_app_number] => 069926 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/069926
Adiabatic dynamic logic May 27, 1993 Issued
Array ( [id] => 3462879 [patent_doc_number] => 05473270 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-05 [patent_title] => 'Adiabatic dynamic precharge boost circuitry' [patent_app_type] => 1 [patent_app_number] => 8/069945 [patent_app_country] => US [patent_app_date] => 1993-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 8993 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/473/05473270.pdf [firstpage_image] =>[orig_patent_app_number] => 069945 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/069945
Adiabatic dynamic precharge boost circuitry May 27, 1993 Issued
Array ( [id] => 3477539 [patent_doc_number] => 05477164 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-19 [patent_title] => 'Adiabatic dynamic noninverting circuitry' [patent_app_type] => 1 [patent_app_number] => 8/069944 [patent_app_country] => US [patent_app_date] => 1993-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 9026 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/477/05477164.pdf [firstpage_image] =>[orig_patent_app_number] => 069944 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/069944
Adiabatic dynamic noninverting circuitry May 27, 1993 Issued
Array ( [id] => 3495549 [patent_doc_number] => 05440242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'CMOS pull-up input network' [patent_app_type] => 1 [patent_app_number] => 8/067226 [patent_app_country] => US [patent_app_date] => 1993-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2187 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/440/05440242.pdf [firstpage_image] =>[orig_patent_app_number] => 067226 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/067226
CMOS pull-up input network May 25, 1993 Issued
Array ( [id] => 3118612 [patent_doc_number] => 05396129 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'Semiconductor integrated circuit apparatus comprising clock signal line formed in a ring shape' [patent_app_type] => 1 [patent_app_number] => 8/066225 [patent_app_country] => US [patent_app_date] => 1993-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6505 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/396/05396129.pdf [firstpage_image] =>[orig_patent_app_number] => 066225 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/066225
Semiconductor integrated circuit apparatus comprising clock signal line formed in a ring shape May 24, 1993 Issued
Array ( [id] => 3461165 [patent_doc_number] => 05402016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-28 [patent_title] => 'Integrated high-speed bipolar logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/066518 [patent_app_country] => US [patent_app_date] => 1993-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3399 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/402/05402016.pdf [firstpage_image] =>[orig_patent_app_number] => 066518 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/066518
Integrated high-speed bipolar logic circuit May 23, 1993 Issued
Array ( [id] => 3124674 [patent_doc_number] => 05381058 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-10 [patent_title] => 'FPGA having PFU with programmable output driver inputs' [patent_app_type] => 1 [patent_app_number] => 8/065823 [patent_app_country] => US [patent_app_date] => 1993-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2550 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/381/05381058.pdf [firstpage_image] =>[orig_patent_app_number] => 065823 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/065823
FPGA having PFU with programmable output driver inputs May 20, 1993 Issued
Array ( [id] => 3058427 [patent_doc_number] => 05345113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-06 [patent_title] => 'Control module for reducing ringing in digital signals on a transmission line' [patent_app_type] => 1 [patent_app_number] => 8/064511 [patent_app_country] => US [patent_app_date] => 1993-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5229 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/345/05345113.pdf [firstpage_image] =>[orig_patent_app_number] => 064511 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/064511
Control module for reducing ringing in digital signals on a transmission line May 18, 1993 Issued
Array ( [id] => 2998902 [patent_doc_number] => 05367205 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'High speed output buffer with reduced voltage bounce and no cross current' [patent_app_type] => 1 [patent_app_number] => 8/061607 [patent_app_country] => US [patent_app_date] => 1993-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2014 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/367/05367205.pdf [firstpage_image] =>[orig_patent_app_number] => 061607 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/061607
High speed output buffer with reduced voltage bounce and no cross current May 12, 1993 Issued
Array ( [id] => 3070449 [patent_doc_number] => 05352941 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-04 [patent_title] => 'CMOS/ECL level converting circuit' [patent_app_type] => 1 [patent_app_number] => 8/058250 [patent_app_country] => US [patent_app_date] => 1993-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4097 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/352/05352941.pdf [firstpage_image] =>[orig_patent_app_number] => 058250 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/058250
CMOS/ECL level converting circuit May 9, 1993 Issued
Array ( [id] => 3124657 [patent_doc_number] => 05381057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-10 [patent_title] => 'ECL gate having active pull-down transistor' [patent_app_type] => 1 [patent_app_number] => 8/058314 [patent_app_country] => US [patent_app_date] => 1993-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 42 [patent_no_of_words] => 8831 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/381/05381057.pdf [firstpage_image] =>[orig_patent_app_number] => 058314 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/058314
ECL gate having active pull-down transistor May 2, 1993 Issued
Array ( [id] => 3100701 [patent_doc_number] => 05298802 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-29 [patent_title] => 'Semiconductor integrated circuit device with a plurality of logic circuits having active pull-down functions' [patent_app_type] => 1 [patent_app_number] => 8/056798 [patent_app_country] => US [patent_app_date] => 1993-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 40 [patent_no_of_words] => 21008 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/298/05298802.pdf [firstpage_image] =>[orig_patent_app_number] => 056798 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/056798
Semiconductor integrated circuit device with a plurality of logic circuits having active pull-down functions May 2, 1993 Issued
Array ( [id] => 3431505 [patent_doc_number] => 05404056 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Semiconductor integrated circuit device with independently operable output buffers' [patent_app_type] => 1 [patent_app_number] => 8/053405 [patent_app_country] => US [patent_app_date] => 1993-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7522 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404056.pdf [firstpage_image] =>[orig_patent_app_number] => 053405 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/053405
Semiconductor integrated circuit device with independently operable output buffers Apr 27, 1993 Issued
Array ( [id] => 3058464 [patent_doc_number] => 05345115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-06 [patent_title] => 'Superconducting input interface circuit for superconducting circuit' [patent_app_type] => 1 [patent_app_number] => 8/053207 [patent_app_country] => US [patent_app_date] => 1993-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2326 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/345/05345115.pdf [firstpage_image] =>[orig_patent_app_number] => 053207 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/053207
Superconducting input interface circuit for superconducting circuit Apr 27, 1993 Issued
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