Search

David R. Hudspeth

Supervisory Patent Examiner (ID: 19114, Phone: (571)272-7843 , Office: P/2657 )

Most Active Art Unit
2504
Art Unit(s)
2651, 2509, 2641, 2657, 2504, 2626, 2681, 2741
Total Applications
1592
Issued Applications
1465
Pending Applications
21
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6701916 [patent_doc_number] => 20030224796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Method of assigning resources that vary in time to provide continuous services and application of the method to telecommunication system planning' [patent_app_type] => new [patent_app_number] => 10/373842 [patent_app_country] => US [patent_app_date] => 2003-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7768 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20030224796.pdf [firstpage_image] =>[orig_patent_app_number] => 10373842 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/373842
Method of assigning resources that vary in time to provide continuous services and application of the method to telecommunication system planning Feb 26, 2003 Abandoned
Array ( [id] => 6098189 [patent_doc_number] => 20020052747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'Method and system of interpreting and presenting web content using a voice browser' [patent_app_type] => new [patent_app_number] => 09/933956 [patent_app_country] => US [patent_app_date] => 2001-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5887 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20020052747.pdf [firstpage_image] =>[orig_patent_app_number] => 09933956 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/933956
Method and system of interpreting and presenting web content using a voice browser Aug 20, 2001 Abandoned
09/831139 Data processing system or communication terminal with a device for recognising speech and method for recognising certain acoustic objects Jun 20, 2001 Abandoned
Array ( [id] => 845833 [patent_doc_number] => 07389220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-17 [patent_title] => 'Correcting incomplete negation errors in French language text' [patent_app_type] => utility [patent_app_number] => 09/809899 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6173 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/389/07389220.pdf [firstpage_image] =>[orig_patent_app_number] => 09809899 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809899
Correcting incomplete negation errors in French language text Mar 15, 2001 Issued
Array ( [id] => 4377805 [patent_doc_number] => 06192337 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Apparatus and methods for rejecting confusible words during training associated with a speech recognition system' [patent_app_type] => 1 [patent_app_number] => 9/134259 [patent_app_country] => US [patent_app_date] => 1998-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6435 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/192/06192337.pdf [firstpage_image] =>[orig_patent_app_number] => 134259 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/134259
Apparatus and methods for rejecting confusible words during training associated with a speech recognition system Aug 13, 1998 Issued
Array ( [id] => 4176078 [patent_doc_number] => 06115597 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Disposal emergency cellular phone' [patent_app_type] => 1 [patent_app_number] => 8/895358 [patent_app_country] => US [patent_app_date] => 1997-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1987 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115597.pdf [firstpage_image] =>[orig_patent_app_number] => 895358 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/895358
Disposal emergency cellular phone Jul 15, 1997 Issued
Array ( [id] => 3693249 [patent_doc_number] => 05696454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Hierarchical programming of electrically configurable integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/788623 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4893 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696454.pdf [firstpage_image] =>[orig_patent_app_number] => 788623 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/788623
Hierarchical programming of electrically configurable integrated circuits Jan 22, 1997 Issued
Array ( [id] => 3742561 [patent_doc_number] => 05698992 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Programmable logic module and architecture for field programmable gate array device' [patent_app_type] => 1 [patent_app_number] => 8/746554 [patent_app_country] => US [patent_app_date] => 1996-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 11970 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/698/05698992.pdf [firstpage_image] =>[orig_patent_app_number] => 746554 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/746554
Programmable logic module and architecture for field programmable gate array device Nov 12, 1996 Issued
Array ( [id] => 3699895 [patent_doc_number] => 05680061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Techniques for programming programmable logic array devices' [patent_app_type] => 1 [patent_app_number] => 8/747194 [patent_app_country] => US [patent_app_date] => 1996-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6047 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680061.pdf [firstpage_image] =>[orig_patent_app_number] => 747194 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/747194
Techniques for programming programmable logic array devices Nov 11, 1996 Issued
Array ( [id] => 3859562 [patent_doc_number] => 05767696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Tri-state devices having exclusive gate output control' [patent_app_type] => 1 [patent_app_number] => 8/742721 [patent_app_country] => US [patent_app_date] => 1996-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2832 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767696.pdf [firstpage_image] =>[orig_patent_app_number] => 742721 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/742721
Tri-state devices having exclusive gate output control Oct 31, 1996 Issued
Array ( [id] => 3836954 [patent_doc_number] => 05760611 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Function generator for programmable gate array' [patent_app_type] => 1 [patent_app_number] => 8/739102 [patent_app_country] => US [patent_app_date] => 1996-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3203 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/760/05760611.pdf [firstpage_image] =>[orig_patent_app_number] => 739102 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/739102
Function generator for programmable gate array Oct 24, 1996 Issued
Array ( [id] => 3836914 [patent_doc_number] => 05760608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'High speed, low clock load register dump circuit' [patent_app_type] => 1 [patent_app_number] => 8/731817 [patent_app_country] => US [patent_app_date] => 1996-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1215 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/760/05760608.pdf [firstpage_image] =>[orig_patent_app_number] => 731817 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/731817
High speed, low clock load register dump circuit Oct 20, 1996 Issued
Array ( [id] => 3863440 [patent_doc_number] => 05705939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors' [patent_app_type] => 1 [patent_app_number] => 8/730351 [patent_app_country] => US [patent_app_date] => 1996-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3757 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 412 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/705/05705939.pdf [firstpage_image] =>[orig_patent_app_number] => 730351 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/730351
Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors Oct 14, 1996 Issued
Array ( [id] => 3777705 [patent_doc_number] => 05773992 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Output buffer circuit capable of supressing ringing' [patent_app_type] => 1 [patent_app_number] => 8/730501 [patent_app_country] => US [patent_app_date] => 1996-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 5193 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/773/05773992.pdf [firstpage_image] =>[orig_patent_app_number] => 730501 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/730501
Output buffer circuit capable of supressing ringing Oct 10, 1996 Issued
Array ( [id] => 3881342 [patent_doc_number] => 05764074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'System for, and method of, minimizing noise in an integrated circuit chip' [patent_app_type] => 1 [patent_app_number] => 8/715234 [patent_app_country] => US [patent_app_date] => 1996-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4688 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764074.pdf [firstpage_image] =>[orig_patent_app_number] => 715234 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/715234
System for, and method of, minimizing noise in an integrated circuit chip Sep 17, 1996 Issued
Array ( [id] => 3764309 [patent_doc_number] => RE035764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Inverting output driver circuit for reducing electron injection into the substrate' [patent_app_type] => 2 [patent_app_number] => 8/713757 [patent_app_country] => US [patent_app_date] => 1996-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2118 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/035/RE035764.pdf [firstpage_image] =>[orig_patent_app_number] => 713757 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/713757
Inverting output driver circuit for reducing electron injection into the substrate Sep 12, 1996 Issued
Array ( [id] => 3654147 [patent_doc_number] => 05640105 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Current mode null convention threshold gate' [patent_app_type] => 1 [patent_app_number] => 8/711560 [patent_app_country] => US [patent_app_date] => 1996-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 52 [patent_no_of_words] => 16730 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/640/05640105.pdf [firstpage_image] =>[orig_patent_app_number] => 711560 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/711560
Current mode null convention threshold gate Sep 9, 1996 Issued
Array ( [id] => 3837645 [patent_doc_number] => 05739700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Method and apparatus with dual circuitry for shifting the level of a signal' [patent_app_type] => 1 [patent_app_number] => 8/709706 [patent_app_country] => US [patent_app_date] => 1996-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3748 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/739/05739700.pdf [firstpage_image] =>[orig_patent_app_number] => 709706 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/709706
Method and apparatus with dual circuitry for shifting the level of a signal Sep 8, 1996 Issued
Array ( [id] => 3666646 [patent_doc_number] => 05656948 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Null convention threshold gate' [patent_app_type] => 1 [patent_app_number] => 8/711232 [patent_app_country] => US [patent_app_date] => 1996-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 52 [patent_no_of_words] => 16711 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/656/05656948.pdf [firstpage_image] =>[orig_patent_app_number] => 711232 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/711232
Null convention threshold gate Sep 8, 1996 Issued
Array ( [id] => 3832645 [patent_doc_number] => 05812982 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Digital data encoding apparatus and method thereof' [patent_app_type] => 1 [patent_app_number] => 8/697728 [patent_app_country] => US [patent_app_date] => 1996-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4029 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812982.pdf [firstpage_image] =>[orig_patent_app_number] => 697728 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/697728
Digital data encoding apparatus and method thereof Aug 28, 1996 Issued
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