Search

David R. Hudspeth

Supervisory Patent Examiner (ID: 19114, Phone: (571)272-7843 , Office: P/2657 )

Most Active Art Unit
2504
Art Unit(s)
2651, 2509, 2641, 2657, 2504, 2626, 2681, 2741
Total Applications
1592
Issued Applications
1465
Pending Applications
21
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3111968 [patent_doc_number] => 05418477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-23 [patent_title] => 'Data output buffer pull-down circuit for TTL interface' [patent_app_type] => 1 [patent_app_number] => 8/052005 [patent_app_country] => US [patent_app_date] => 1993-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3203 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/418/05418477.pdf [firstpage_image] =>[orig_patent_app_number] => 052005 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/052005
Data output buffer pull-down circuit for TTL interface Apr 21, 1993 Issued
Array ( [id] => 3479565 [patent_doc_number] => 05428302 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-27 [patent_title] => 'Logic circuit with controlled current supply output' [patent_app_type] => 1 [patent_app_number] => 8/052200 [patent_app_country] => US [patent_app_date] => 1993-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 5957 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/428/05428302.pdf [firstpage_image] =>[orig_patent_app_number] => 052200 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/052200
Logic circuit with controlled current supply output Apr 21, 1993 Issued
Array ( [id] => 3425924 [patent_doc_number] => 05389837 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Superconducting flux flow digital circuits' [patent_app_type] => 1 [patent_app_number] => 8/051103 [patent_app_country] => US [patent_app_date] => 1993-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3569 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/389/05389837.pdf [firstpage_image] =>[orig_patent_app_number] => 051103 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/051103
Superconducting flux flow digital circuits Apr 20, 1993 Issued
Array ( [id] => 3458489 [patent_doc_number] => 05378943 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Low power interface circuit' [patent_app_type] => 1 [patent_app_number] => 8/049912 [patent_app_country] => US [patent_app_date] => 1993-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5018 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/378/05378943.pdf [firstpage_image] =>[orig_patent_app_number] => 049912 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/049912
Low power interface circuit Apr 19, 1993 Issued
Array ( [id] => 3461111 [patent_doc_number] => 05402012 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-28 [patent_title] => 'Sequentially clocked domino-logic cells' [patent_app_type] => 1 [patent_app_number] => 8/048671 [patent_app_country] => US [patent_app_date] => 1993-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5678 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/402/05402012.pdf [firstpage_image] =>[orig_patent_app_number] => 048671 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/048671
Sequentially clocked domino-logic cells Apr 18, 1993 Issued
Array ( [id] => 3017152 [patent_doc_number] => 05332936 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-26 [patent_title] => 'Composite logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/045708 [patent_app_country] => US [patent_app_date] => 1993-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6722 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/332/05332936.pdf [firstpage_image] =>[orig_patent_app_number] => 045708 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/045708
Composite logic circuit Apr 13, 1993 Issued
Array ( [id] => 3017134 [patent_doc_number] => 05332935 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-26 [patent_title] => 'ECL and TTL to CMOS logic converter' [patent_app_type] => 1 [patent_app_number] => 8/045101 [patent_app_country] => US [patent_app_date] => 1993-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2283 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/332/05332935.pdf [firstpage_image] =>[orig_patent_app_number] => 045101 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/045101
ECL and TTL to CMOS logic converter Apr 11, 1993 Issued
Array ( [id] => 3100793 [patent_doc_number] => 05298805 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-29 [patent_title] => 'Versatile and efficient cell-to-local bus interface in a configurable logic array' [patent_app_type] => 1 [patent_app_number] => 8/044921 [patent_app_country] => US [patent_app_date] => 1993-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 49 [patent_no_of_words] => 11384 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/298/05298805.pdf [firstpage_image] =>[orig_patent_app_number] => 044921 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/044921
Versatile and efficient cell-to-local bus interface in a configurable logic array Apr 7, 1993 Issued
Array ( [id] => 2889197 [patent_doc_number] => 05268598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-07 [patent_title] => 'High-density erasable programmable logic device architecture using multiplexer interconnections' [patent_app_type] => 1 [patent_app_number] => 8/043146 [patent_app_country] => US [patent_app_date] => 1993-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6591 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/268/05268598.pdf [firstpage_image] =>[orig_patent_app_number] => 043146 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/043146
High-density erasable programmable logic device architecture using multiplexer interconnections Mar 30, 1993 Issued
Array ( [id] => 3061934 [patent_doc_number] => 05350954 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-27 [patent_title] => 'Macrocell with flexible product term allocation' [patent_app_type] => 1 [patent_app_number] => 8/039927 [patent_app_country] => US [patent_app_date] => 1993-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3131 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/350/05350954.pdf [firstpage_image] =>[orig_patent_app_number] => 039927 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/039927
Macrocell with flexible product term allocation Mar 28, 1993 Issued
Array ( [id] => 3069182 [patent_doc_number] => 05311080 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-10 [patent_title] => 'Field programmable gate array with direct input/output connection' [patent_app_type] => 1 [patent_app_number] => 8/037766 [patent_app_country] => US [patent_app_date] => 1993-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2607 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/311/05311080.pdf [firstpage_image] =>[orig_patent_app_number] => 037766 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/037766
Field programmable gate array with direct input/output connection Mar 25, 1993 Issued
Array ( [id] => 3012877 [patent_doc_number] => 05355032 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-11 [patent_title] => 'TTL to CMOS translator circuit and method' [patent_app_type] => 1 [patent_app_number] => 8/036613 [patent_app_country] => US [patent_app_date] => 1993-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3317 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/355/05355032.pdf [firstpage_image] =>[orig_patent_app_number] => 036613 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/036613
TTL to CMOS translator circuit and method Mar 23, 1993 Issued
08/035554 APPLICATION SPECIFIC EXCLUSIVE OR BASED LOGIC MODULE ARCHITECTURE FOR FPGA'S Mar 22, 1993 Pending
Array ( [id] => 3038646 [patent_doc_number] => 05329185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-12 [patent_title] => 'CMOS logic circuitry providing improved operating speed' [patent_app_type] => 1 [patent_app_number] => 8/035127 [patent_app_country] => US [patent_app_date] => 1993-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1585 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/329/05329185.pdf [firstpage_image] =>[orig_patent_app_number] => 035127 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/035127
CMOS logic circuitry providing improved operating speed Mar 18, 1993 Issued
Array ( [id] => 3485840 [patent_doc_number] => 05406139 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-11 [patent_title] => 'Input buffer utilizing a cascode to provide a zero power TTL to CMOS input with high speed switching' [patent_app_type] => 1 [patent_app_number] => 8/034510 [patent_app_country] => US [patent_app_date] => 1993-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3381 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/406/05406139.pdf [firstpage_image] =>[orig_patent_app_number] => 034510 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/034510
Input buffer utilizing a cascode to provide a zero power TTL to CMOS input with high speed switching Mar 18, 1993 Issued
Array ( [id] => 3007115 [patent_doc_number] => 05371420 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-06 [patent_title] => 'Output circuit having reduced switching noise' [patent_app_type] => 1 [patent_app_number] => 8/035115 [patent_app_country] => US [patent_app_date] => 1993-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 60 [patent_no_of_words] => 26865 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/371/05371420.pdf [firstpage_image] =>[orig_patent_app_number] => 035115 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/035115
Output circuit having reduced switching noise Mar 18, 1993 Issued
Array ( [id] => 3104502 [patent_doc_number] => 05315175 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-24 [patent_title] => 'Quasi-differential bus' [patent_app_type] => 1 [patent_app_number] => 8/033222 [patent_app_country] => US [patent_app_date] => 1993-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1344 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/315/05315175.pdf [firstpage_image] =>[orig_patent_app_number] => 033222 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/033222
Quasi-differential bus Mar 17, 1993 Issued
Array ( [id] => 3023451 [patent_doc_number] => 05302866 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-12 [patent_title] => 'Input circuit block and method for PLDs with register clock enable selection' [patent_app_type] => 1 [patent_app_number] => 8/032919 [patent_app_country] => US [patent_app_date] => 1993-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/302/05302866.pdf [firstpage_image] =>[orig_patent_app_number] => 032919 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/032919
Input circuit block and method for PLDs with register clock enable selection Mar 17, 1993 Issued
Array ( [id] => 3000236 [patent_doc_number] => 05362999 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-08 [patent_title] => 'EPLD chip with hybrid architecture optimized for both speed and flexibility' [patent_app_type] => 1 [patent_app_number] => 8/032920 [patent_app_country] => US [patent_app_date] => 1993-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3323 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/362/05362999.pdf [firstpage_image] =>[orig_patent_app_number] => 032920 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/032920
EPLD chip with hybrid architecture optimized for both speed and flexibility Mar 17, 1993 Issued
08/030625 CHARGE RECOVERY LOGIC Mar 11, 1993 Pending
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