
David R. Hudspeth
Supervisory Patent Examiner (ID: 19114, Phone: (571)272-7843 , Office: P/2657 )
| Most Active Art Unit | 2504 |
| Art Unit(s) | 2651, 2509, 2641, 2657, 2504, 2626, 2681, 2741 |
| Total Applications | 1592 |
| Issued Applications | 1465 |
| Pending Applications | 21 |
| Abandoned Applications | 105 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3032339
[patent_doc_number] => 05317214
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-31
[patent_title] => 'Interface circuit having differential signal common mode shifting means'
[patent_app_type] => 1
[patent_app_number] => 8/028511
[patent_app_country] => US
[patent_app_date] => 1993-03-09
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[pdf_file] => patents/05/317/05317214.pdf
[firstpage_image] =>[orig_patent_app_number] => 028511
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/028511 | Interface circuit having differential signal common mode shifting means | Mar 8, 1993 | Issued |
Array
(
[id] => 3495593
[patent_doc_number] => 05440245
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-08
[patent_title] => 'Logic module with configurable combinational and sequential blocks'
[patent_app_type] => 1
[patent_app_number] => 8/028789
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[firstpage_image] =>[orig_patent_app_number] => 028789
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/028789 | Logic module with configurable combinational and sequential blocks | Mar 8, 1993 | Issued |
Array
(
[id] => 3038569
[patent_doc_number] => 05329181
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[patent_kind] => NA
[patent_issue_date] => 1994-07-12
[patent_title] => 'Complementary macrocell feedback circuit'
[patent_app_type] => 1
[patent_app_number] => 8/027211
[patent_app_country] => US
[patent_app_date] => 1993-03-05
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[firstpage_image] =>[orig_patent_app_number] => 027211
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/027211 | Complementary macrocell feedback circuit | Mar 4, 1993 | Issued |
Array
(
[id] => 3006992
[patent_doc_number] => 05371413
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-06
[patent_title] => 'Process and arrangement for the Boolean realization of adaline-type neural networks'
[patent_app_type] => 1
[patent_app_number] => 7/983531
[patent_app_country] => US
[patent_app_date] => 1993-03-04
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 4028
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[pdf_file] => patents/05/371/05371413.pdf
[firstpage_image] =>[orig_patent_app_number] => 983531
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/983531 | Process and arrangement for the Boolean realization of adaline-type neural networks | Mar 3, 1993 | Issued |
Array
(
[id] => 3087488
[patent_doc_number] => 05280202
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-18
[patent_title] => 'Programmable application specific integrated circuit and logic cell therefor'
[patent_app_type] => 1
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[patent_app_date] => 1993-03-02
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[pdf_file] => patents/05/280/05280202.pdf
[firstpage_image] =>[orig_patent_app_number] => 024986
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/024986 | Programmable application specific integrated circuit and logic cell therefor | Mar 1, 1993 | Issued |
Array
(
[id] => 3041001
[patent_doc_number] => 05300824
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-05
[patent_title] => 'Integrated circuit with improved on-chip power supply control'
[patent_app_type] => 1
[patent_app_number] => 8/024924
[patent_app_country] => US
[patent_app_date] => 1993-02-26
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[pdf_file] => patents/05/300/05300824.pdf
[firstpage_image] =>[orig_patent_app_number] => 024924
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/024924 | Integrated circuit with improved on-chip power supply control | Feb 25, 1993 | Issued |
Array
(
[id] => 3032271
[patent_doc_number] => 05317210
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-31
[patent_title] => 'I/O cell for programmable logic device providing latched, unlatched, and fast inputs'
[patent_app_type] => 1
[patent_app_number] => 8/021414
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/317/05317210.pdf
[firstpage_image] =>[orig_patent_app_number] => 021414
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/021414 | I/O cell for programmable logic device providing latched, unlatched, and fast inputs | Feb 22, 1993 | Issued |
Array
(
[id] => 3025403
[patent_doc_number] => 05327026
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-05
[patent_title] => 'Self-timed bootstrap decoder'
[patent_app_type] => 1
[patent_app_number] => 8/018802
[patent_app_country] => US
[patent_app_date] => 1993-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => patents/05/327/05327026.pdf
[firstpage_image] =>[orig_patent_app_number] => 018802
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/018802 | Self-timed bootstrap decoder | Feb 16, 1993 | Issued |
Array
(
[id] => 3050015
[patent_doc_number] => 05287018
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-15
[patent_title] => 'Dynamic PLA time circuit'
[patent_app_type] => 1
[patent_app_number] => 8/018360
[patent_app_country] => US
[patent_app_date] => 1993-02-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/287/05287018.pdf
[firstpage_image] =>[orig_patent_app_number] => 018360
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/018360 | Dynamic PLA time circuit | Feb 15, 1993 | Issued |
| 08/015726 | A TRISTATE DRIVER FOR INTERFACING TO A BUS SUBJECT TO OVERVOLTAGE CONDITIONS | Feb 9, 1993 | Abandoned |
Array
(
[id] => 3062082
[patent_doc_number] => 05338978
[patent_country] => US
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[patent_issue_date] => 1994-08-16
[patent_title] => 'Full swing power down buffer circuit with multiple power supply isolation'
[patent_app_type] => 1
[patent_app_number] => 8/016009
[patent_app_country] => US
[patent_app_date] => 1993-02-10
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/338/05338978.pdf
[firstpage_image] =>[orig_patent_app_number] => 016009
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/016009 | Full swing power down buffer circuit with multiple power supply isolation | Feb 9, 1993 | Issued |
Array
(
[id] => 3101568
[patent_doc_number] => 05319255
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[patent_kind] => NA
[patent_issue_date] => 1994-06-07
[patent_title] => 'Power up detect circuit for configurable logic array'
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[patent_app_number] => 8/015412
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[patent_app_date] => 1993-02-09
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[firstpage_image] =>[orig_patent_app_number] => 015412
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/015412 | Power up detect circuit for configurable logic array | Feb 8, 1993 | Issued |
Array
(
[id] => 3020091
[patent_doc_number] => 05341040
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[patent_issue_date] => 1994-08-23
[patent_title] => 'High performance output buffer with reduced ground bounce'
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[patent_app_number] => 8/015371
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Array
(
[id] => 3569491
[patent_doc_number] => 05483176
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Array
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[id] => 3038553
[patent_doc_number] => 05329180
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[patent_issue_date] => 1994-07-12
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[firstpage_image] =>[orig_patent_app_number] => 015347
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Array
(
[id] => 3076303
[patent_doc_number] => 05336950
[patent_country] => US
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[patent_issue_date] => 1994-08-09
[patent_title] => 'Configuration features in a configurable logic array'
[patent_app_type] => 1
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[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/015415 | Configuration features in a configurable logic array | Feb 7, 1993 | Issued |
| 08/015466 | DIRECT I/O ACCESS TO EXPRESS BUSSING IN A CONFIGURABLE LOGIC ARRAY | Feb 7, 1993 | Abandoned |
| 08/013780 | DIAGONAL WIRING BETWEEN ABUTTING LOGIC CELLS IN A CONFIGURATION LOGIC ARRAY | Feb 4, 1993 | Abandoned |
Array
(
[id] => 3032252
[patent_doc_number] => 05317209
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[patent_title] => 'Dynamic three-state bussing capability in a configurable logic array'
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[pdf_file] => patents/05/317/05317209.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/014464 | Dynamic three-state bussing capability in a configurable logic array | Feb 4, 1993 | Issued |
Array
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