Search

David R. Hudspeth

Supervisory Patent Examiner (ID: 19114, Phone: (571)272-7843 , Office: P/2657 )

Most Active Art Unit
2504
Art Unit(s)
2651, 2509, 2641, 2657, 2504, 2626, 2681, 2741
Total Applications
1592
Issued Applications
1465
Pending Applications
21
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3425895 [patent_doc_number] => 05389835 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Vector logic method and dynamic mousetrap logic gate for a self-timed monotonic logic progression' [patent_app_type] => 1 [patent_app_number] => 8/014881 [patent_app_country] => US [patent_app_date] => 1993-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9142 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 23 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/389/05389835.pdf [firstpage_image] =>[orig_patent_app_number] => 014881 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/014881
Vector logic method and dynamic mousetrap logic gate for a self-timed monotonic logic progression Feb 2, 1993 Issued
Array ( [id] => 3034806 [patent_doc_number] => 05343091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-30 [patent_title] => 'Semiconductor logic integrated circuit having improved noise margin over DCFL circuits' [patent_app_type] => 1 [patent_app_number] => 8/011155 [patent_app_country] => US [patent_app_date] => 1993-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 8738 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/343/05343091.pdf [firstpage_image] =>[orig_patent_app_number] => 011155 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/011155
Semiconductor logic integrated circuit having improved noise margin over DCFL circuits Jan 28, 1993 Issued
Array ( [id] => 3084096 [patent_doc_number] => 05321324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-14 [patent_title] => 'Low-to-high voltage translator with latch-up immunity' [patent_app_type] => 1 [patent_app_number] => 8/010342 [patent_app_country] => US [patent_app_date] => 1993-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 7640 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/321/05321324.pdf [firstpage_image] =>[orig_patent_app_number] => 010342 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/010342
Low-to-high voltage translator with latch-up immunity Jan 27, 1993 Issued
Array ( [id] => 3003240 [patent_doc_number] => 05359242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-25 [patent_title] => 'Programmable logic with carry-in/carry-out between logic blocks' [patent_app_type] => 1 [patent_app_number] => 8/006321 [patent_app_country] => US [patent_app_date] => 1993-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3794 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/359/05359242.pdf [firstpage_image] =>[orig_patent_app_number] => 006321 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/006321
Programmable logic with carry-in/carry-out between logic blocks Jan 20, 1993 Issued
Array ( [id] => 3017096 [patent_doc_number] => 05332933 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-26 [patent_title] => 'Bipolar-MOS circuits with dimensions scaled to enhance performance' [patent_app_type] => 1 [patent_app_number] => 8/006418 [patent_app_country] => US [patent_app_date] => 1993-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4080 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/332/05332933.pdf [firstpage_image] =>[orig_patent_app_number] => 006418 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/006418
Bipolar-MOS circuits with dimensions scaled to enhance performance Jan 20, 1993 Issued
Array ( [id] => 3041175 [patent_doc_number] => 05300833 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Low voltage biCMOS circuit having ECL and TTL input buffers and no intervening level-shift circuits' [patent_app_type] => 1 [patent_app_number] => 8/004995 [patent_app_country] => US [patent_app_date] => 1993-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2115 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/300/05300833.pdf [firstpage_image] =>[orig_patent_app_number] => 004995 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/004995
Low voltage biCMOS circuit having ECL and TTL input buffers and no intervening level-shift circuits Jan 14, 1993 Issued
Array ( [id] => 2998954 [patent_doc_number] => 05367208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'Reconfigurable programmable interconnect architecture' [patent_app_type] => 1 [patent_app_number] => 8/002873 [patent_app_country] => US [patent_app_date] => 1993-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 4791 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/367/05367208.pdf [firstpage_image] =>[orig_patent_app_number] => 002873 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/002873
Reconfigurable programmable interconnect architecture Jan 12, 1993 Issued
Array ( [id] => 3017114 [patent_doc_number] => 05332934 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-26 [patent_title] => 'Small to full swing conversion circuit' [patent_app_type] => 1 [patent_app_number] => 8/000430 [patent_app_country] => US [patent_app_date] => 1993-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3706 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/332/05332934.pdf [firstpage_image] =>[orig_patent_app_number] => 000430 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/000430
Small to full swing conversion circuit Jan 3, 1993 Issued
90/002916 PROGRAMMABLE LOGIC ARRAY DEVICE USING EPROM TECHNOLOGY Dec 30, 1992 Issued
Array ( [id] => 3080349 [patent_doc_number] => 05296757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Low-noise output driver having separate supply lines and sequenced operation for transient and steady-state portions' [patent_app_type] => 1 [patent_app_number] => 7/998922 [patent_app_country] => US [patent_app_date] => 1992-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 31 [patent_no_of_words] => 6393 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/296/05296757.pdf [firstpage_image] =>[orig_patent_app_number] => 998922 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/998922
Low-noise output driver having separate supply lines and sequenced operation for transient and steady-state portions Dec 29, 1992 Issued
Array ( [id] => 3101644 [patent_doc_number] => 05319259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-07 [patent_title] => 'Low voltage input and output circuits with overvoltage protection' [patent_app_type] => 1 [patent_app_number] => 7/994783 [patent_app_country] => US [patent_app_date] => 1992-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 5193 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/319/05319259.pdf [firstpage_image] =>[orig_patent_app_number] => 994783 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/994783
Low voltage input and output circuits with overvoltage protection Dec 21, 1992 Issued
Array ( [id] => 3098385 [patent_doc_number] => 05291080 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-01 [patent_title] => 'Integrated circuit device having tristate input buffer for reducing internal power use' [patent_app_type] => 1 [patent_app_number] => 7/994310 [patent_app_country] => US [patent_app_date] => 1992-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1749 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/291/05291080.pdf [firstpage_image] =>[orig_patent_app_number] => 994310 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/994310
Integrated circuit device having tristate input buffer for reducing internal power use Dec 20, 1992 Issued
Array ( [id] => 3694901 [patent_doc_number] => 05604417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 7/992448 [patent_app_country] => US [patent_app_date] => 1992-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 80 [patent_no_of_words] => 33656 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604417.pdf [firstpage_image] =>[orig_patent_app_number] => 992448 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/992448
Semiconductor integrated circuit device Dec 16, 1992 Issued
Array ( [id] => 3069161 [patent_doc_number] => 05311079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-10 [patent_title] => 'Low power, high performance PLA' [patent_app_type] => 1 [patent_app_number] => 7/992216 [patent_app_country] => US [patent_app_date] => 1992-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3308 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/311/05311079.pdf [firstpage_image] =>[orig_patent_app_number] => 992216 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/992216
Low power, high performance PLA Dec 16, 1992 Issued
Array ( [id] => 3055096 [patent_doc_number] => 05324991 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-28 [patent_title] => 'Neuron unit and neuron unit network' [patent_app_type] => 1 [patent_app_number] => 7/989605 [patent_app_country] => US [patent_app_date] => 1992-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 45 [patent_no_of_words] => 16955 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/324/05324991.pdf [firstpage_image] =>[orig_patent_app_number] => 989605 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/989605
Neuron unit and neuron unit network Dec 10, 1992 Issued
Array ( [id] => 3098406 [patent_doc_number] => 05369317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-29 [patent_title] => 'Circuit and method for controlling the potential of a digit line and in limiting said potential to a maximum value' [patent_app_type] => 1 [patent_app_number] => 7/989252 [patent_app_country] => US [patent_app_date] => 1992-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 4837 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/369/05369317.pdf [firstpage_image] =>[orig_patent_app_number] => 989252 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/989252
Circuit and method for controlling the potential of a digit line and in limiting said potential to a maximum value Dec 10, 1992 Issued
Array ( [id] => 2893967 [patent_doc_number] => 05239212 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-24 [patent_title] => 'Gate circuit of combined field-effect and bipolar transistors with an improved discharge arrangement' [patent_app_type] => 1 [patent_app_number] => 7/986891 [patent_app_country] => US [patent_app_date] => 1992-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 5972 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/239/05239212.pdf [firstpage_image] =>[orig_patent_app_number] => 986891 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/986891
Gate circuit of combined field-effect and bipolar transistors with an improved discharge arrangement Dec 7, 1992 Issued
Array ( [id] => 3041316 [patent_doc_number] => 05300840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Redundancy fuse reading circuit for integrated memory' [patent_app_type] => 1 [patent_app_number] => 7/979534 [patent_app_country] => US [patent_app_date] => 1992-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3947 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/300/05300840.pdf [firstpage_image] =>[orig_patent_app_number] => 979534 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/979534
Redundancy fuse reading circuit for integrated memory Nov 22, 1992 Issued
Array ( [id] => 2894025 [patent_doc_number] => 05239215 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-24 [patent_title] => 'Large scale integrated circuit configured to eliminate clock signal skew effects' [patent_app_type] => 1 [patent_app_number] => 7/980413 [patent_app_country] => US [patent_app_date] => 1992-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4580 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/239/05239215.pdf [firstpage_image] =>[orig_patent_app_number] => 980413 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/980413
Large scale integrated circuit configured to eliminate clock signal skew effects Nov 19, 1992 Issued
Array ( [id] => 3012950 [patent_doc_number] => 05355036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-11 [patent_title] => 'Timed make-before-break circuit for analog switch control' [patent_app_type] => 1 [patent_app_number] => 7/975025 [patent_app_country] => US [patent_app_date] => 1992-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2100 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/355/05355036.pdf [firstpage_image] =>[orig_patent_app_number] => 975025 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/975025
Timed make-before-break circuit for analog switch control Nov 11, 1992 Issued
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