Search

David R. Hudspeth

Supervisory Patent Examiner (ID: 19114, Phone: (571)272-7843 , Office: P/2657 )

Most Active Art Unit
2504
Art Unit(s)
2651, 2509, 2641, 2657, 2504, 2626, 2681, 2741
Total Applications
1592
Issued Applications
1465
Pending Applications
21
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3069107 [patent_doc_number] => 05311076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-10 [patent_title] => 'Tristate data output buffer having reduced switching noise and intermediate-level setting' [patent_app_type] => 1 [patent_app_number] => 7/964622 [patent_app_country] => US [patent_app_date] => 1992-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 15 [patent_no_of_words] => 4214 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/311/05311076.pdf [firstpage_image] =>[orig_patent_app_number] => 964622 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/964622
Tristate data output buffer having reduced switching noise and intermediate-level setting Oct 22, 1992 Issued
Array ( [id] => 3012788 [patent_doc_number] => 05355028 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-11 [patent_title] => 'Lower power CMOS buffer amplifier for use in integrated circuit substrate bias generators' [patent_app_type] => 1 [patent_app_number] => 7/965801 [patent_app_country] => US [patent_app_date] => 1992-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5094 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/355/05355028.pdf [firstpage_image] =>[orig_patent_app_number] => 965801 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/965801
Lower power CMOS buffer amplifier for use in integrated circuit substrate bias generators Oct 22, 1992 Issued
Array ( [id] => 3034843 [patent_doc_number] => 05343093 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-30 [patent_title] => 'Self referencing MOS to ECL level conversion circuit' [patent_app_type] => 1 [patent_app_number] => 7/962422 [patent_app_country] => US [patent_app_date] => 1992-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 4436 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/343/05343093.pdf [firstpage_image] =>[orig_patent_app_number] => 962422 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/962422
Self referencing MOS to ECL level conversion circuit Oct 15, 1992 Issued
Array ( [id] => 3060445 [patent_doc_number] => 05357154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-18 [patent_title] => 'Level converter circuit for converting ECL-level input signals' [patent_app_type] => 1 [patent_app_number] => 7/960814 [patent_app_country] => US [patent_app_date] => 1992-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3325 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/357/05357154.pdf [firstpage_image] =>[orig_patent_app_number] => 960814 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/960814
Level converter circuit for converting ECL-level input signals Oct 13, 1992 Issued
Array ( [id] => 3090788 [patent_doc_number] => 05285117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-08 [patent_title] => 'Output circuit with output enabling inputs' [patent_app_type] => 1 [patent_app_number] => 7/957403 [patent_app_country] => US [patent_app_date] => 1992-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 42 [patent_no_of_words] => 7476 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/285/05285117.pdf [firstpage_image] =>[orig_patent_app_number] => 957403 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/957403
Output circuit with output enabling inputs Oct 5, 1992 Issued
07/957091 HIGH-DENSITY ERASABLE PROGRAMMABLE LOGIC DEVICE ARCHITECTURE USING MULTIPLEXER INTERCONNECTIONS Oct 5, 1992 Abandoned
Array ( [id] => 3038535 [patent_doc_number] => 05329179 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-12 [patent_title] => 'Arrangement for parallel programming of in-system programmable IC logical devices' [patent_app_type] => 1 [patent_app_number] => 7/957311 [patent_app_country] => US [patent_app_date] => 1992-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4203 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/329/05329179.pdf [firstpage_image] =>[orig_patent_app_number] => 957311 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/957311
Arrangement for parallel programming of in-system programmable IC logical devices Oct 4, 1992 Issued
Array ( [id] => 2905216 [patent_doc_number] => 05218240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-08 [patent_title] => 'Programmable logic cell and array with bus repeaters' [patent_app_type] => 1 [patent_app_number] => 7/935116 [patent_app_country] => US [patent_app_date] => 1992-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 4702 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/218/05218240.pdf [firstpage_image] =>[orig_patent_app_number] => 935116 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/935116
Programmable logic cell and array with bus repeaters Aug 24, 1992 Issued
Array ( [id] => 2916685 [patent_doc_number] => 05237214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-17 [patent_title] => 'High speed logic circuit and semiconductor integrated circuit device including variable impedance to provide reduced power consumption' [patent_app_type] => 1 [patent_app_number] => 7/929917 [patent_app_country] => US [patent_app_date] => 1992-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 28 [patent_no_of_words] => 14092 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/237/05237214.pdf [firstpage_image] =>[orig_patent_app_number] => 929917 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/929917
High speed logic circuit and semiconductor integrated circuit device including variable impedance to provide reduced power consumption Aug 16, 1992 Issued
Array ( [id] => 3593860 [patent_doc_number] => 05517129 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'High-speed dual-buffered output circuit' [patent_app_type] => 1 [patent_app_number] => 7/920911 [patent_app_country] => US [patent_app_date] => 1992-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2649 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/517/05517129.pdf [firstpage_image] =>[orig_patent_app_number] => 920911 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/920911
High-speed dual-buffered output circuit Jul 27, 1992 Issued
Array ( [id] => 2896988 [patent_doc_number] => 05270585 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-14 [patent_title] => 'Output driver stage with two tier current limit protection' [patent_app_type] => 1 [patent_app_number] => 7/919324 [patent_app_country] => US [patent_app_date] => 1992-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3115 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/270/05270585.pdf [firstpage_image] =>[orig_patent_app_number] => 919324 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/919324
Output driver stage with two tier current limit protection Jul 26, 1992 Issued
Array ( [id] => 3041055 [patent_doc_number] => 05300827 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Noise immune NTL logic network' [patent_app_type] => 1 [patent_app_number] => 7/920401 [patent_app_country] => US [patent_app_date] => 1992-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1128 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/300/05300827.pdf [firstpage_image] =>[orig_patent_app_number] => 920401 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/920401
Noise immune NTL logic network Jul 26, 1992 Issued
Array ( [id] => 3052450 [patent_doc_number] => 05304871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-19 [patent_title] => 'Programmable interconnect architecture employing leaky programmable elements' [patent_app_type] => 1 [patent_app_number] => 7/919605 [patent_app_country] => US [patent_app_date] => 1992-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5704 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/304/05304871.pdf [firstpage_image] =>[orig_patent_app_number] => 919605 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/919605
Programmable interconnect architecture employing leaky programmable elements Jul 23, 1992 Issued
Array ( [id] => 3012292 [patent_doc_number] => 05331226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-19 [patent_title] => 'Logic cell for field programmable gate array having optional input inverters' [patent_app_type] => 1 [patent_app_number] => 7/919812 [patent_app_country] => US [patent_app_date] => 1992-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 69 [patent_no_of_words] => 13058 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/331/05331226.pdf [firstpage_image] =>[orig_patent_app_number] => 919812 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/919812
Logic cell for field programmable gate array having optional input inverters Jul 22, 1992 Issued
07/919076 INTEGRATED CIRCUIT WITH IMPROVED ON-CHIP POWER SUPPLY CONTROL Jul 22, 1992 Abandoned
Array ( [id] => 3098363 [patent_doc_number] => 05291079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-01 [patent_title] => 'Configuration control unit for programming a field programmable gate array and reading array status' [patent_app_type] => 1 [patent_app_number] => 7/919407 [patent_app_country] => US [patent_app_date] => 1992-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 70 [patent_no_of_words] => 12949 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/291/05291079.pdf [firstpage_image] =>[orig_patent_app_number] => 919407 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/919407
Configuration control unit for programming a field programmable gate array and reading array status Jul 22, 1992 Issued
Array ( [id] => 3104629 [patent_doc_number] => 05315182 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-24 [patent_title] => 'Semiconductor integrated circuit having annular power supply with plural lines' [patent_app_type] => 1 [patent_app_number] => 7/918525 [patent_app_country] => US [patent_app_date] => 1992-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 32 [patent_no_of_words] => 9592 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/315/05315182.pdf [firstpage_image] =>[orig_patent_app_number] => 918525 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/918525
Semiconductor integrated circuit having annular power supply with plural lines Jul 22, 1992 Issued
Array ( [id] => 3020266 [patent_doc_number] => 05341049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Integrated circuit having alternate rows of logic cells and I/O cells' [patent_app_type] => 1 [patent_app_number] => 7/916430 [patent_app_country] => US [patent_app_date] => 1992-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 13973 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/341/05341049.pdf [firstpage_image] =>[orig_patent_app_number] => 916430 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/916430
Integrated circuit having alternate rows of logic cells and I/O cells Jul 20, 1992 Issued
Array ( [id] => 3080406 [patent_doc_number] => 05296760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Voltage translator' [patent_app_type] => 1 [patent_app_number] => 7/914731 [patent_app_country] => US [patent_app_date] => 1992-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2120 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/296/05296760.pdf [firstpage_image] =>[orig_patent_app_number] => 914731 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/914731
Voltage translator Jul 19, 1992 Issued
Array ( [id] => 3090806 [patent_doc_number] => 05285118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-08 [patent_title] => 'Complementary current tree decoder' [patent_app_type] => 1 [patent_app_number] => 7/914830 [patent_app_country] => US [patent_app_date] => 1992-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2331 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/285/05285118.pdf [firstpage_image] =>[orig_patent_app_number] => 914830 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/914830
Complementary current tree decoder Jul 15, 1992 Issued
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