| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3097758
[patent_doc_number] => 05313117
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-17
[patent_title] => 'Semiconductor logic circuit using two n-type negative resistance devices'
[patent_app_type] => 1
[patent_app_number] => 7/913108
[patent_app_country] => US
[patent_app_date] => 1992-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 27
[patent_no_of_words] => 5027
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/313/05313117.pdf
[firstpage_image] =>[orig_patent_app_number] => 913108
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/913108 | Semiconductor logic circuit using two n-type negative resistance devices | Jul 13, 1992 | Issued |
Array
(
[id] => 3087524
[patent_doc_number] => 05280204
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-18
[patent_title] => 'ECI compatible CMOS off-chip driver using feedback to set output levels'
[patent_app_type] => 1
[patent_app_number] => 7/907906
[patent_app_country] => US
[patent_app_date] => 1992-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1907
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/280/05280204.pdf
[firstpage_image] =>[orig_patent_app_number] => 907906
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/907906 | ECI compatible CMOS off-chip driver using feedback to set output levels | Jul 1, 1992 | Issued |
Array
(
[id] => 3025384
[patent_doc_number] => 05327024
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-05
[patent_title] => 'Field programmable antifuse device and programming method therefor'
[patent_app_type] => 1
[patent_app_number] => 7/907904
[patent_app_country] => US
[patent_app_date] => 1992-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 4215
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/327/05327024.pdf
[firstpage_image] =>[orig_patent_app_number] => 907904
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/907904 | Field programmable antifuse device and programming method therefor | Jul 1, 1992 | Issued |
Array
(
[id] => 3015437
[patent_doc_number] => 05281869
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-25
[patent_title] => 'Reduced-voltage NMOS output driver'
[patent_app_type] => 1
[patent_app_number] => 7/907402
[patent_app_country] => US
[patent_app_date] => 1992-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 3342
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/281/05281869.pdf
[firstpage_image] =>[orig_patent_app_number] => 907402
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/907402 | Reduced-voltage NMOS output driver | Jun 30, 1992 | Issued |
Array
(
[id] => 3100720
[patent_doc_number] => 05293083
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-08
[patent_title] => 'Fast limited swing push-pull driver'
[patent_app_type] => 1
[patent_app_number] => 7/906811
[patent_app_country] => US
[patent_app_date] => 1992-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1208
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/293/05293083.pdf
[firstpage_image] =>[orig_patent_app_number] => 906811
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/906811 | Fast limited swing push-pull driver | Jun 29, 1992 | Issued |
Array
(
[id] => 2967176
[patent_doc_number] => 05274276
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-12-28
[patent_title] => 'Output driver circuit comprising a programmable circuit for determining the potential at the output node and the method of implementing the circuit'
[patent_app_type] => 1
[patent_app_number] => 7/904814
[patent_app_country] => US
[patent_app_date] => 1992-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 3822
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/274/05274276.pdf
[firstpage_image] =>[orig_patent_app_number] => 904814
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/904814 | Output driver circuit comprising a programmable circuit for determining the potential at the output node and the method of implementing the circuit | Jun 25, 1992 | Issued |
| 07/904913 | OUTPUT DRIVER CIRCUIT COMPRISING A REGULATOR CIRCUIT FOR DETERMINING THE POTENTIAL AT THE OUTPUT NODE AND THE METHOD OF IMPLEMENTING THE CIRCUIT | Jun 25, 1992 | Abandoned |
Array
(
[id] => 2989984
[patent_doc_number] => 05250860
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-05
[patent_title] => 'Three-level cascode differential current switch'
[patent_app_type] => 1
[patent_app_number] => 7/904125
[patent_app_country] => US
[patent_app_date] => 1992-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 1702
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/250/05250860.pdf
[firstpage_image] =>[orig_patent_app_number] => 904125
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/904125 | Three-level cascode differential current switch | Jun 24, 1992 | Issued |
Array
(
[id] => 2949204
[patent_doc_number] => 05254886
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-19
[patent_title] => 'Clock distribution scheme for user-programmable logic array architecture'
[patent_app_type] => 1
[patent_app_number] => 7/901604
[patent_app_country] => US
[patent_app_date] => 1992-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3214
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 246
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/254/05254886.pdf
[firstpage_image] =>[orig_patent_app_number] => 901604
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/901604 | Clock distribution scheme for user-programmable logic array architecture | Jun 18, 1992 | Issued |
Array
(
[id] => 2967962
[patent_doc_number] => 05264741
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-23
[patent_title] => 'Low current, fast, CMOS static pullup circuit for static random-access memories'
[patent_app_type] => 1
[patent_app_number] => 7/901603
[patent_app_country] => US
[patent_app_date] => 1992-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 4335
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/264/05264741.pdf
[firstpage_image] =>[orig_patent_app_number] => 901603
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/901603 | Low current, fast, CMOS static pullup circuit for static random-access memories | Jun 18, 1992 | Issued |
Array
(
[id] => 2949221
[patent_doc_number] => 05254887
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-19
[patent_title] => 'ECL to BiCMIS level converter'
[patent_app_type] => 1
[patent_app_number] => 7/900421
[patent_app_country] => US
[patent_app_date] => 1992-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 2970
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/254/05254887.pdf
[firstpage_image] =>[orig_patent_app_number] => 900421
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/900421 | ECL to BiCMIS level converter | Jun 17, 1992 | Issued |
Array
(
[id] => 2943542
[patent_doc_number] => 05191241
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-02
[patent_title] => 'Programmable interconnect architecture'
[patent_app_type] => 1
[patent_app_number] => 7/899729
[patent_app_country] => US
[patent_app_date] => 1992-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3331
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/191/05191241.pdf
[firstpage_image] =>[orig_patent_app_number] => 899729
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/899729 | Programmable interconnect architecture | Jun 16, 1992 | Issued |
Array
(
[id] => 3025405
[patent_doc_number] => 05289056
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-22
[patent_title] => 'BICMOS input buffer circuit with integral passgate'
[patent_app_type] => 1
[patent_app_number] => 7/898029
[patent_app_country] => US
[patent_app_date] => 1992-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3111
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/289/05289056.pdf
[firstpage_image] =>[orig_patent_app_number] => 898029
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/898029 | BICMOS input buffer circuit with integral passgate | Jun 11, 1992 | Issued |
Array
(
[id] => 2908585
[patent_doc_number] => 05248906
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-09-28
[patent_title] => 'High speed CMOS output buffer circuit minimizes output signal oscillation and steady state current'
[patent_app_type] => 1
[patent_app_number] => 7/897736
[patent_app_country] => US
[patent_app_date] => 1992-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 6502
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/248/05248906.pdf
[firstpage_image] =>[orig_patent_app_number] => 897736
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/897736 | High speed CMOS output buffer circuit minimizes output signal oscillation and steady state current | Jun 11, 1992 | Issued |
Array
(
[id] => 2891039
[patent_doc_number] => 05214320
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-05-25
[patent_title] => 'System and method for reducing ground bounce in integrated circuit output buffers'
[patent_app_type] => 1
[patent_app_number] => 7/897729
[patent_app_country] => US
[patent_app_date] => 1992-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 5740
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/214/05214320.pdf
[firstpage_image] =>[orig_patent_app_number] => 897729
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/897729 | System and method for reducing ground bounce in integrated circuit output buffers | Jun 11, 1992 | Issued |
Array
(
[id] => 2916153
[patent_doc_number] => 05227677
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-07-13
[patent_title] => 'Zero power transmission line terminator'
[patent_app_type] => 1
[patent_app_number] => 7/896719
[patent_app_country] => US
[patent_app_date] => 1992-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3535
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/227/05227677.pdf
[firstpage_image] =>[orig_patent_app_number] => 896719
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/896719 | Zero power transmission line terminator | Jun 9, 1992 | Issued |
Array
(
[id] => 2981339
[patent_doc_number] => 05256911
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-26
[patent_title] => 'Neural network with multiplexed snyaptic processing'
[patent_app_type] => 1
[patent_app_number] => 7/896204
[patent_app_country] => US
[patent_app_date] => 1992-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 4168
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/256/05256911.pdf
[firstpage_image] =>[orig_patent_app_number] => 896204
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/896204 | Neural network with multiplexed snyaptic processing | Jun 9, 1992 | Issued |
Array
(
[id] => 3093217
[patent_doc_number] => 05278464
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-11
[patent_title] => 'Using delay to obtain high speed current driver circuit'
[patent_app_type] => 1
[patent_app_number] => 7/892834
[patent_app_country] => US
[patent_app_date] => 1992-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 3472
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/278/05278464.pdf
[firstpage_image] =>[orig_patent_app_number] => 892834
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/892834 | Using delay to obtain high speed current driver circuit | Jun 1, 1992 | Issued |
| 07/886000 | SELF-TIMED CLOCKING SYSTEM AND METHOD FOR SELF-TIMED DYNAMIC LOGIC CIRCUITS | May 18, 1992 | Abandoned |
Array
(
[id] => 2939966
[patent_doc_number] => 05247206
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-09-21
[patent_title] => 'Neural network accommodating parallel synaptic weight adjustments in a single cycle'
[patent_app_type] => 1
[patent_app_number] => 7/885528
[patent_app_country] => US
[patent_app_date] => 1992-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 6578
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/247/05247206.pdf
[firstpage_image] =>[orig_patent_app_number] => 885528
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/885528 | Neural network accommodating parallel synaptic weight adjustments in a single cycle | May 18, 1992 | Issued |