Search

David R. Hudspeth

Supervisory Patent Examiner (ID: 19114, Phone: (571)272-7843 , Office: P/2657 )

Most Active Art Unit
2504
Art Unit(s)
2651, 2509, 2641, 2657, 2504, 2626, 2681, 2741
Total Applications
1592
Issued Applications
1465
Pending Applications
21
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2980664 [patent_doc_number] => 05225719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix' [patent_app_type] => 1 [patent_app_number] => 7/699427 [patent_app_country] => US [patent_app_date] => 1991-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 117 [patent_figures_cnt] => 131 [patent_no_of_words] => 27180 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/225/05225719.pdf [firstpage_image] =>[orig_patent_app_number] => 699427 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/699427
Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix May 12, 1991 Issued
Array ( [id] => 2946678 [patent_doc_number] => 05223750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-29 [patent_title] => 'Artificial neural function circuit having organic thin film elements' [patent_app_type] => 1 [patent_app_number] => 7/698148 [patent_app_country] => US [patent_app_date] => 1991-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3336 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/223/05223750.pdf [firstpage_image] =>[orig_patent_app_number] => 698148 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/698148
Artificial neural function circuit having organic thin film elements May 9, 1991 Issued
Array ( [id] => 2834599 [patent_doc_number] => 05099143 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-24 [patent_title] => 'Dual voltage supply circuit with multiplier-controlled transistor' [patent_app_type] => 1 [patent_app_number] => 7/697205 [patent_app_country] => US [patent_app_date] => 1991-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 11605 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/099/05099143.pdf [firstpage_image] =>[orig_patent_app_number] => 697205 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/697205
Dual voltage supply circuit with multiplier-controlled transistor May 7, 1991 Issued
Array ( [id] => 2790150 [patent_doc_number] => 05130574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-14 [patent_title] => 'Programmable logic device providing product term sharing and steering to the outputs of the programmable logic device' [patent_app_type] => 1 [patent_app_number] => 7/696461 [patent_app_country] => US [patent_app_date] => 1991-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3284 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/130/05130574.pdf [firstpage_image] =>[orig_patent_app_number] => 696461 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/696461
Programmable logic device providing product term sharing and steering to the outputs of the programmable logic device May 5, 1991 Issued
Array ( [id] => 2943578 [patent_doc_number] => 05191243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-02 [patent_title] => 'Output logic macrocell with enhanced functional capabilities' [patent_app_type] => 1 [patent_app_number] => 7/696907 [patent_app_country] => US [patent_app_date] => 1991-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4159 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/191/05191243.pdf [firstpage_image] =>[orig_patent_app_number] => 696907 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/696907
Output logic macrocell with enhanced functional capabilities May 5, 1991 Issued
Array ( [id] => 2916759 [patent_doc_number] => 05237218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-17 [patent_title] => 'Structure and method for multiplexing pins for in-system programming' [patent_app_type] => 1 [patent_app_number] => 7/695356 [patent_app_country] => US [patent_app_date] => 1991-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 8 [patent_no_of_words] => 3877 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/237/05237218.pdf [firstpage_image] =>[orig_patent_app_number] => 695356 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/695356
Structure and method for multiplexing pins for in-system programming May 2, 1991 Issued
Array ( [id] => 2847003 [patent_doc_number] => 05138198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-11 [patent_title] => 'Integrated programmable logic device with control circuit to power down unused sense amplifiers' [patent_app_type] => 1 [patent_app_number] => 7/695180 [patent_app_country] => US [patent_app_date] => 1991-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3285 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 728 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/138/05138198.pdf [firstpage_image] =>[orig_patent_app_number] => 695180 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/695180
Integrated programmable logic device with control circuit to power down unused sense amplifiers May 2, 1991 Issued
Array ( [id] => 2806684 [patent_doc_number] => 05124588 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-23 [patent_title] => 'Programmable combinational logic circuit' [patent_app_type] => 1 [patent_app_number] => 7/695036 [patent_app_country] => US [patent_app_date] => 1991-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5299 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/124/05124588.pdf [firstpage_image] =>[orig_patent_app_number] => 695036 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/695036
Programmable combinational logic circuit Apr 30, 1991 Issued
Array ( [id] => 2788813 [patent_doc_number] => 05142167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-25 [patent_title] => 'Encoding for simultaneous switching output noise reduction' [patent_app_type] => 1 [patent_app_number] => 7/694178 [patent_app_country] => US [patent_app_date] => 1991-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4326 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/142/05142167.pdf [firstpage_image] =>[orig_patent_app_number] => 694178 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/694178
Encoding for simultaneous switching output noise reduction Apr 30, 1991 Issued
Array ( [id] => 2923306 [patent_doc_number] => 05206541 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-27 [patent_title] => 'Current-mode based analog circuits for synthetic neural systems' [patent_app_type] => 1 [patent_app_number] => 7/693310 [patent_app_country] => US [patent_app_date] => 1991-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 6344 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/206/05206541.pdf [firstpage_image] =>[orig_patent_app_number] => 693310 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/693310
Current-mode based analog circuits for synthetic neural systems Apr 29, 1991 Issued
Array ( [id] => 2806540 [patent_doc_number] => 05124580 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-23 [patent_title] => 'BiCMOS logic gate having linearly operated load FETs' [patent_app_type] => 1 [patent_app_number] => 7/693815 [patent_app_country] => US [patent_app_date] => 1991-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3785 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/124/05124580.pdf [firstpage_image] =>[orig_patent_app_number] => 693815 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/693815
BiCMOS logic gate having linearly operated load FETs Apr 29, 1991 Issued
Array ( [id] => 2863684 [patent_doc_number] => 05149992 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-22 [patent_title] => 'MOS folded source-coupled logic' [patent_app_type] => 1 [patent_app_number] => 7/693532 [patent_app_country] => US [patent_app_date] => 1991-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2333 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/149/05149992.pdf [firstpage_image] =>[orig_patent_app_number] => 693532 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/693532
MOS folded source-coupled logic Apr 29, 1991 Issued
Array ( [id] => 2899658 [patent_doc_number] => 05184032 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-02 [patent_title] => 'Glitch reduction in integrated circuits, systems and methods' [patent_app_type] => 1 [patent_app_number] => 7/691266 [patent_app_country] => US [patent_app_date] => 1991-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 4805 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/184/05184032.pdf [firstpage_image] =>[orig_patent_app_number] => 691266 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/691266
Glitch reduction in integrated circuits, systems and methods Apr 24, 1991 Issued
Array ( [id] => 2835744 [patent_doc_number] => 05175445 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-29 [patent_title] => 'MOS type input circuit' [patent_app_type] => 1 [patent_app_number] => 7/691414 [patent_app_country] => US [patent_app_date] => 1991-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 41 [patent_no_of_words] => 8961 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/175/05175445.pdf [firstpage_image] =>[orig_patent_app_number] => 691414 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/691414
MOS type input circuit Apr 24, 1991 Issued
Array ( [id] => 2899830 [patent_doc_number] => 05241224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-31 [patent_title] => 'High-density erasable programmable logic device architecture using multiplexer interconnections' [patent_app_type] => 1 [patent_app_number] => 7/691640 [patent_app_country] => US [patent_app_date] => 1991-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6566 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/241/05241224.pdf [firstpage_image] =>[orig_patent_app_number] => 691640 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/691640
High-density erasable programmable logic device architecture using multiplexer interconnections Apr 24, 1991 Issued
Array ( [id] => 2806705 [patent_doc_number] => 05124589 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-23 [patent_title] => 'Semiconductor integrated circuit capable of synchronous and asynchronous operations and operating method therefor' [patent_app_type] => 1 [patent_app_number] => 7/691615 [patent_app_country] => US [patent_app_date] => 1991-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 19984 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/124/05124589.pdf [firstpage_image] =>[orig_patent_app_number] => 691615 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/691615
Semiconductor integrated circuit capable of synchronous and asynchronous operations and operating method therefor Apr 24, 1991 Issued
Array ( [id] => 2803323 [patent_doc_number] => 05140178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-18 [patent_title] => 'Reset circuit for microcomputer' [patent_app_type] => 1 [patent_app_number] => 7/690757 [patent_app_country] => US [patent_app_date] => 1991-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2296 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/140/05140178.pdf [firstpage_image] =>[orig_patent_app_number] => 690757 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/690757
Reset circuit for microcomputer Apr 23, 1991 Issued
Array ( [id] => 2840827 [patent_doc_number] => 05121006 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-09 [patent_title] => 'Registered logic macrocell with product term allocation and adjacent product term stealing' [patent_app_type] => 1 [patent_app_number] => 7/688252 [patent_app_country] => US [patent_app_date] => 1991-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2213 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/121/05121006.pdf [firstpage_image] =>[orig_patent_app_number] => 688252 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/688252
Registered logic macrocell with product term allocation and adjacent product term stealing Apr 21, 1991 Issued
Array ( [id] => 2856657 [patent_doc_number] => 05126595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-30 [patent_title] => 'BI-MOS semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 7/689707 [patent_app_country] => US [patent_app_date] => 1991-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2948 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/126/05126595.pdf [firstpage_image] =>[orig_patent_app_number] => 689707 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/689707
BI-MOS semiconductor integrated circuit Apr 18, 1991 Issued
Array ( [id] => 2778754 [patent_doc_number] => 05132567 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-21 [patent_title] => 'Low threshold BiCMOS circuit' [patent_app_type] => 1 [patent_app_number] => 7/687341 [patent_app_country] => US [patent_app_date] => 1991-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1680 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/132/05132567.pdf [firstpage_image] =>[orig_patent_app_number] => 687341 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/687341
Low threshold BiCMOS circuit Apr 17, 1991 Issued
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