Search

David R. Hudspeth

Supervisory Patent Examiner (ID: 19114, Phone: (571)272-7843 , Office: P/2657 )

Most Active Art Unit
2504
Art Unit(s)
2651, 2509, 2641, 2657, 2504, 2626, 2681, 2741
Total Applications
1592
Issued Applications
1465
Pending Applications
21
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2713360 [patent_doc_number] => 05061866 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-29 [patent_title] => 'Analog, continuous time vector scalar multiplier circuits and programmable feedback neural network using them' [patent_app_type] => 1 [patent_app_number] => 7/564027 [patent_app_country] => US [patent_app_date] => 1990-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3964 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/061/05061866.pdf [firstpage_image] =>[orig_patent_app_number] => 564027 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/564027
Analog, continuous time vector scalar multiplier circuits and programmable feedback neural network using them Aug 5, 1990 Issued
Array ( [id] => 2697723 [patent_doc_number] => 05065040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-12 [patent_title] => 'Reverse flow neuron' [patent_app_type] => 1 [patent_app_number] => 7/562169 [patent_app_country] => US [patent_app_date] => 1990-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6135 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/065/05065040.pdf [firstpage_image] =>[orig_patent_app_number] => 562169 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/562169
Reverse flow neuron Aug 2, 1990 Issued
Array ( [id] => 2829953 [patent_doc_number] => 05095347 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-10 [patent_title] => 'Plural transistor silicon on insulator structure with shared electrodes' [patent_app_type] => 1 [patent_app_number] => 7/561385 [patent_app_country] => US [patent_app_date] => 1990-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4144 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/095/05095347.pdf [firstpage_image] =>[orig_patent_app_number] => 561385 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/561385
Plural transistor silicon on insulator structure with shared electrodes Jul 31, 1990 Issued
Array ( [id] => 2778735 [patent_doc_number] => 05132566 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-21 [patent_title] => 'BiMOS semiconductor integrated circuit having short-circuit protection' [patent_app_type] => 1 [patent_app_number] => 7/557990 [patent_app_country] => US [patent_app_date] => 1990-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3298 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 386 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/132/05132566.pdf [firstpage_image] =>[orig_patent_app_number] => 557990 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/557990
BiMOS semiconductor integrated circuit having short-circuit protection Jul 24, 1990 Issued
Array ( [id] => 3055275 [patent_doc_number] => 05283480 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-01 [patent_title] => 'Semiconductor integrated circuit device with a plurality of logic circuits having active pull-down functions' [patent_app_type] => 1 [patent_app_number] => 7/557109 [patent_app_country] => US [patent_app_date] => 1990-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 40 [patent_no_of_words] => 21023 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/283/05283480.pdf [firstpage_image] =>[orig_patent_app_number] => 557109 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/557109
Semiconductor integrated circuit device with a plurality of logic circuits having active pull-down functions Jul 24, 1990 Issued
Array ( [id] => 2710302 [patent_doc_number] => 04992679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-12 [patent_title] => 'Programming logic device with multiple independent feedbacks per input/output terminal' [patent_app_type] => 1 [patent_app_number] => 7/555364 [patent_app_country] => US [patent_app_date] => 1990-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 9585 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/992/04992679.pdf [firstpage_image] =>[orig_patent_app_number] => 555364 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/555364
Programming logic device with multiple independent feedbacks per input/output terminal Jul 15, 1990 Issued
Array ( [id] => 2718634 [patent_doc_number] => 05053647 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-01 [patent_title] => 'Programmable logic array having feedback flip-flops connected between a product array\'s inputs and its outputs' [patent_app_type] => 1 [patent_app_number] => 7/552671 [patent_app_country] => US [patent_app_date] => 1990-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7427 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/053/05053647.pdf [firstpage_image] =>[orig_patent_app_number] => 552671 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/552671
Programmable logic array having feedback flip-flops connected between a product array's inputs and its outputs Jul 15, 1990 Issued
07/536688 AUTOMATIC POLARITY SWITCHING OUTPUT CIRCUIT Jul 9, 1990 Abandoned
Array ( [id] => 2859553 [patent_doc_number] => 05113093 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-12 [patent_title] => 'Semiconductor integrated circuit with multiple operation' [patent_app_type] => 1 [patent_app_number] => 7/550604 [patent_app_country] => US [patent_app_date] => 1990-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3369 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/113/05113093.pdf [firstpage_image] =>[orig_patent_app_number] => 550604 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/550604
Semiconductor integrated circuit with multiple operation Jul 9, 1990 Issued
Array ( [id] => 2852109 [patent_doc_number] => 05111079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-05 [patent_title] => 'Power reduction circuit for programmable logic device' [patent_app_type] => 1 [patent_app_number] => 7/545921 [patent_app_country] => US [patent_app_date] => 1990-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 2139 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/111/05111079.pdf [firstpage_image] =>[orig_patent_app_number] => 545921 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/545921
Power reduction circuit for programmable logic device Jun 28, 1990 Issued
Array ( [id] => 2806667 [patent_doc_number] => 05124587 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-23 [patent_title] => 'Integrated circuit with a configuration circuit' [patent_app_type] => 1 [patent_app_number] => 7/547605 [patent_app_country] => US [patent_app_date] => 1990-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 3101 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/124/05124587.pdf [firstpage_image] =>[orig_patent_app_number] => 547605 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/547605
Integrated circuit with a configuration circuit Jun 27, 1990 Issued
Array ( [id] => 2750811 [patent_doc_number] => 05015882 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-14 [patent_title] => 'Compound domino CMOS circuit' [patent_app_type] => 1 [patent_app_number] => 7/542666 [patent_app_country] => US [patent_app_date] => 1990-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 8 [patent_no_of_words] => 4635 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/015/05015882.pdf [firstpage_image] =>[orig_patent_app_number] => 542666 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/542666
Compound domino CMOS circuit Jun 24, 1990 Issued
Array ( [id] => 2675741 [patent_doc_number] => 05073729 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-17 [patent_title] => 'Segmented routing architecture' [patent_app_type] => 1 [patent_app_number] => 7/542722 [patent_app_country] => US [patent_app_date] => 1990-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2508 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/073/05073729.pdf [firstpage_image] =>[orig_patent_app_number] => 542722 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/542722
Segmented routing architecture Jun 21, 1990 Issued
07/540049 DIGITAL COMPUTER HAVING A SYSTEM FOR SEQUENTIALLY REFRESHING AN EXPANDABLE DYNAMIC RAM MEMORY CIRCUIT Jun 18, 1990 Abandoned
Array ( [id] => 2697944 [patent_doc_number] => 05065052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-12 [patent_title] => 'Arbiter circuit using plural-reset RS flip-flops' [patent_app_type] => 1 [patent_app_number] => 7/538244 [patent_app_country] => US [patent_app_date] => 1990-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4674 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/065/05065052.pdf [firstpage_image] =>[orig_patent_app_number] => 538244 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/538244
Arbiter circuit using plural-reset RS flip-flops Jun 13, 1990 Issued
Array ( [id] => 2684899 [patent_doc_number] => 05066872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-19 [patent_title] => 'Speed-up technique for a constant di/dt buffer' [patent_app_type] => 1 [patent_app_number] => 7/535815 [patent_app_country] => US [patent_app_date] => 1990-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2094 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/066/05066872.pdf [firstpage_image] =>[orig_patent_app_number] => 535815 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/535815
Speed-up technique for a constant di/dt buffer Jun 10, 1990 Issued
Array ( [id] => 2737110 [patent_doc_number] => 05039871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-13 [patent_title] => 'Capacitive structures for weighted summation as used in neural nets' [patent_app_type] => 1 [patent_app_number] => 7/526470 [patent_app_country] => US [patent_app_date] => 1990-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 21635 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/039/05039871.pdf [firstpage_image] =>[orig_patent_app_number] => 526470 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/526470
Capacitive structures for weighted summation as used in neural nets May 20, 1990 Issued
Array ( [id] => 2737091 [patent_doc_number] => 05039870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-13 [patent_title] => 'Weighted summation circuits having different-weight ranks of capacitive structures' [patent_app_type] => 1 [patent_app_number] => 7/525931 [patent_app_country] => US [patent_app_date] => 1990-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 21469 [patent_no_of_claims] => 76 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/039/05039870.pdf [firstpage_image] =>[orig_patent_app_number] => 525931 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/525931
Weighted summation circuits having different-weight ranks of capacitive structures May 20, 1990 Issued
Array ( [id] => 2747134 [patent_doc_number] => 05028810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-02 [patent_title] => 'Four quadrant synapse cell employing single column summing line' [patent_app_type] => 1 [patent_app_number] => 7/526070 [patent_app_country] => US [patent_app_date] => 1990-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 7669 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/028/05028810.pdf [firstpage_image] =>[orig_patent_app_number] => 526070 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/526070
Four quadrant synapse cell employing single column summing line May 17, 1990 Issued
Array ( [id] => 2685982 [patent_doc_number] => 05045726 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-03 [patent_title] => 'Low power programming circuit for user programmable digital logic array' [patent_app_type] => 1 [patent_app_number] => 7/524329 [patent_app_country] => US [patent_app_date] => 1990-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2921 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 452 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/045/05045726.pdf [firstpage_image] =>[orig_patent_app_number] => 524329 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/524329
Low power programming circuit for user programmable digital logic array May 15, 1990 Issued
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