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David R. Hudspeth

Supervisory Patent Examiner (ID: 19114, Phone: (571)272-7843 , Office: P/2657 )

Most Active Art Unit
2504
Art Unit(s)
2651, 2509, 2641, 2657, 2504, 2626, 2681, 2741
Total Applications
1592
Issued Applications
1465
Pending Applications
21
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2749501 [patent_doc_number] => 04987325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-22 [patent_title] => 'Mode selecting circuit for semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/379240 [patent_app_country] => US [patent_app_date] => 1989-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3596 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/987/04987325.pdf [firstpage_image] =>[orig_patent_app_number] => 379240 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/379240
Mode selecting circuit for semiconductor memory device Jul 12, 1989 Issued
Array ( [id] => 2567409 [patent_doc_number] => 04945265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-31 [patent_title] => 'ECL/CML pseudo-rail circuit, cutoff driver circuit, and latch circuit' [patent_app_type] => 1 [patent_app_number] => 7/379088 [patent_app_country] => US [patent_app_date] => 1989-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4750 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/945/04945265.pdf [firstpage_image] =>[orig_patent_app_number] => 379088 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/379088
ECL/CML pseudo-rail circuit, cutoff driver circuit, and latch circuit Jul 12, 1989 Issued
Array ( [id] => 2593540 [patent_doc_number] => 04970417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-11-13 [patent_title] => 'Emitter coupled logic latch circuit' [patent_app_type] => 1 [patent_app_number] => 7/374294 [patent_app_country] => US [patent_app_date] => 1989-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 11171 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/970/04970417.pdf [firstpage_image] =>[orig_patent_app_number] => 374294 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/374294
Emitter coupled logic latch circuit Jun 29, 1989 Issued
Array ( [id] => 2628776 [patent_doc_number] => 04956569 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-11 [patent_title] => 'CMOS logic circuit for high voltage operation' [patent_app_type] => 1 [patent_app_number] => 7/373203 [patent_app_country] => US [patent_app_date] => 1989-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 2368 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/956/04956569.pdf [firstpage_image] =>[orig_patent_app_number] => 373203 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/373203
CMOS logic circuit for high voltage operation Jun 29, 1989 Issued
Array ( [id] => 2749307 [patent_doc_number] => 05003201 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-26 [patent_title] => 'Option/sequence selection circuit with sequence selection first' [patent_app_type] => 1 [patent_app_number] => 7/372605 [patent_app_country] => US [patent_app_date] => 1989-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1916 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/003/05003201.pdf [firstpage_image] =>[orig_patent_app_number] => 372605 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/372605
Option/sequence selection circuit with sequence selection first Jun 27, 1989 Issued
Array ( [id] => 2636229 [patent_doc_number] => 04958094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-18 [patent_title] => 'Emitter follower circuit with MOSFET' [patent_app_type] => 1 [patent_app_number] => 7/391605 [patent_app_country] => US [patent_app_date] => 1989-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2053 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/958/04958094.pdf [firstpage_image] =>[orig_patent_app_number] => 391605 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/391605
Emitter follower circuit with MOSFET Jun 27, 1989 Issued
Array ( [id] => 2684503 [patent_doc_number] => 05004932 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-02 [patent_title] => 'Unit circuit for constructing a neural network and a semiconductor integrated circuit having the same' [patent_app_type] => 1 [patent_app_number] => 7/373261 [patent_app_country] => US [patent_app_date] => 1989-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4942 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/004/05004932.pdf [firstpage_image] =>[orig_patent_app_number] => 373261 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/373261
Unit circuit for constructing a neural network and a semiconductor integrated circuit having the same Jun 26, 1989 Issued
07/370155 DIFFERENTIATING LOGICAL CIRCUIT FOR ASYNCHRONOUS SYSTEMS Jun 21, 1989 Abandoned
Array ( [id] => 2636123 [patent_doc_number] => 04958088 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-18 [patent_title] => 'Low power three-stage CMOS input buffer with controlled switching' [patent_app_type] => 1 [patent_app_number] => 7/368405 [patent_app_country] => US [patent_app_date] => 1989-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 768 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/958/04958088.pdf [firstpage_image] =>[orig_patent_app_number] => 368405 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/368405
Low power three-stage CMOS input buffer with controlled switching Jun 18, 1989 Issued
Array ( [id] => 2672054 [patent_doc_number] => 04935648 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-06-19 [patent_title] => 'Optimized E.sup.2 pal cell for minimum read disturb' [patent_app_type] => 1 [patent_app_number] => 7/351011 [patent_app_country] => US [patent_app_date] => 1989-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 7031 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/935/04935648.pdf [firstpage_image] =>[orig_patent_app_number] => 351011 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/351011
Optimized E.sup.2 pal cell for minimum read disturb Jun 15, 1989 Issued
Array ( [id] => 2699699 [patent_doc_number] => 04990801 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-05 [patent_title] => 'Internal timing circuit for a CMOS programmable logic array' [patent_app_type] => 1 [patent_app_number] => 7/366830 [patent_app_country] => US [patent_app_date] => 1989-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4145 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/990/04990801.pdf [firstpage_image] =>[orig_patent_app_number] => 366830 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/366830
Internal timing circuit for a CMOS programmable logic array Jun 14, 1989 Issued
07/359703 DATA OUTPUT BUFFER USING A JUNCTION FIELD EFFECT TRANSISTOR May 30, 1989 Abandoned
Array ( [id] => 2703079 [patent_doc_number] => 04988902 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-29 [patent_title] => 'Semiconductor transmission gate with capacitance compensation' [patent_app_type] => 1 [patent_app_number] => 7/356086 [patent_app_country] => US [patent_app_date] => 1989-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 6415 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/988/04988902.pdf [firstpage_image] =>[orig_patent_app_number] => 356086 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/356086
Semiconductor transmission gate with capacitance compensation May 23, 1989 Issued
07/355726 PROGRAMMABLE LOGIC DEVICE HAVING EXPANDED LOGIC CAPABILITY May 22, 1989 Abandoned
07/351971 BASE CELL FOR SEMI-CUSTOM CIRCUIT WITH MERGED TECHNOLOGY May 14, 1989 Abandoned
Array ( [id] => 2640629 [patent_doc_number] => RE033378 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-09 [patent_title] => 'Incremental base drive circuit for a power transistor' [patent_app_type] => 2 [patent_app_number] => 7/352158 [patent_app_country] => US [patent_app_date] => 1989-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1903 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/033/RE033378.pdf [firstpage_image] =>[orig_patent_app_number] => 352158 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/352158
Incremental base drive circuit for a power transistor May 14, 1989 Issued
Array ( [id] => 2561725 [patent_doc_number] => 04942317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-17 [patent_title] => 'Master slice type semiconductor integrated circuit having 2 or more I/O cells per connection pad' [patent_app_type] => 1 [patent_app_number] => 7/351001 [patent_app_country] => US [patent_app_date] => 1989-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2163 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/942/04942317.pdf [firstpage_image] =>[orig_patent_app_number] => 351001 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/351001
Master slice type semiconductor integrated circuit having 2 or more I/O cells per connection pad May 11, 1989 Issued
Array ( [id] => 2597928 [patent_doc_number] => 04940909 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-10 [patent_title] => 'Configuration control circuit for programmable logic devices' [patent_app_type] => 1 [patent_app_number] => 7/351485 [patent_app_country] => US [patent_app_date] => 1989-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5541 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/940/04940909.pdf [firstpage_image] =>[orig_patent_app_number] => 351485 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/351485
Configuration control circuit for programmable logic devices May 11, 1989 Issued
Array ( [id] => 2749651 [patent_doc_number] => 05012135 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-30 [patent_title] => 'Logic gates with a programmable number of inputs' [patent_app_type] => 1 [patent_app_number] => 7/351437 [patent_app_country] => US [patent_app_date] => 1989-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4468 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/012/05012135.pdf [firstpage_image] =>[orig_patent_app_number] => 351437 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/351437
Logic gates with a programmable number of inputs May 11, 1989 Issued
Array ( [id] => 2630943 [patent_doc_number] => 04967107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-30 [patent_title] => 'Programmable logic expander' [patent_app_type] => 1 [patent_app_number] => 7/351840 [patent_app_country] => US [patent_app_date] => 1989-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7666 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/967/04967107.pdf [firstpage_image] =>[orig_patent_app_number] => 351840 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/351840
Programmable logic expander May 11, 1989 Issued
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