Search

David R. Hudspeth

Supervisory Patent Examiner (ID: 19114, Phone: (571)272-7843 , Office: P/2657 )

Most Active Art Unit
2504
Art Unit(s)
2651, 2509, 2641, 2657, 2504, 2626, 2681, 2741
Total Applications
1592
Issued Applications
1465
Pending Applications
21
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3894376 [patent_doc_number] => 05723987 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Level shifting output buffer with p channel pulldown transistors which are bypassed' [patent_app_type] => 1 [patent_app_number] => 8/660607 [patent_app_country] => US [patent_app_date] => 1996-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3421 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/723/05723987.pdf [firstpage_image] =>[orig_patent_app_number] => 660607 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/660607
Level shifting output buffer with p channel pulldown transistors which are bypassed Jun 5, 1996 Issued
Array ( [id] => 3848454 [patent_doc_number] => 05708372 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Semiconductor device with electromagnetic radiation reduced' [patent_app_type] => 1 [patent_app_number] => 8/658411 [patent_app_country] => US [patent_app_date] => 1996-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4153 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708372.pdf [firstpage_image] =>[orig_patent_app_number] => 658411 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/658411
Semiconductor device with electromagnetic radiation reduced Jun 4, 1996 Issued
08/658537 TECHNIQUES FOR PROGRAMMING PROGRAMMABLE LOGIC ARRAY DEVICES Jun 4, 1996 Abandoned
Array ( [id] => 3894363 [patent_doc_number] => 05723986 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Level shifting circuit' [patent_app_type] => 1 [patent_app_number] => 8/659000 [patent_app_country] => US [patent_app_date] => 1996-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4224 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/723/05723986.pdf [firstpage_image] =>[orig_patent_app_number] => 659000 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/659000
Level shifting circuit Jun 3, 1996 Issued
Array ( [id] => 3792383 [patent_doc_number] => 05736867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Method and circuit for reconfiguring a buffer' [patent_app_type] => 1 [patent_app_number] => 8/658671 [patent_app_country] => US [patent_app_date] => 1996-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5819 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/736/05736867.pdf [firstpage_image] =>[orig_patent_app_number] => 658671 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/658671
Method and circuit for reconfiguring a buffer Jun 3, 1996 Issued
Array ( [id] => 3634674 [patent_doc_number] => 05686844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'Integrated circuit pins configurable as a clock input pin and as a digital I/O pin or as a device reset pin and as a digital I/O pin and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/644915 [patent_app_country] => US [patent_app_date] => 1996-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3468 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/686/05686844.pdf [firstpage_image] =>[orig_patent_app_number] => 644915 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/644915
Integrated circuit pins configurable as a clock input pin and as a digital I/O pin or as a device reset pin and as a digital I/O pin and method therefor May 23, 1996 Issued
Array ( [id] => 3799069 [patent_doc_number] => 05726585 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Switching circuit for use in a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/651801 [patent_app_country] => US [patent_app_date] => 1996-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 1653 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726585.pdf [firstpage_image] =>[orig_patent_app_number] => 651801 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/651801
Switching circuit for use in a semiconductor memory device May 23, 1996 Issued
Array ( [id] => 3898775 [patent_doc_number] => 05724287 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Data input circuit of semiconductor storage device' [patent_app_type] => 1 [patent_app_number] => 8/651716 [patent_app_country] => US [patent_app_date] => 1996-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7277 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/724/05724287.pdf [firstpage_image] =>[orig_patent_app_number] => 651716 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/651716
Data input circuit of semiconductor storage device May 21, 1996 Issued
Array ( [id] => 3791089 [patent_doc_number] => 05821771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Method and apparatus for monitoring or forcing an internal node in a programmable device' [patent_app_type] => 1 [patent_app_number] => 8/651101 [patent_app_country] => US [patent_app_date] => 1996-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3478 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/821/05821771.pdf [firstpage_image] =>[orig_patent_app_number] => 651101 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/651101
Method and apparatus for monitoring or forcing an internal node in a programmable device May 20, 1996 Issued
Array ( [id] => 4055712 [patent_doc_number] => 05869979 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Technique for preconditioning I/Os during reconfiguration' [patent_app_type] => 1 [patent_app_number] => 8/647102 [patent_app_country] => US [patent_app_date] => 1996-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/869/05869979.pdf [firstpage_image] =>[orig_patent_app_number] => 647102 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/647102
Technique for preconditioning I/Os during reconfiguration May 8, 1996 Issued
Array ( [id] => 3782465 [patent_doc_number] => 05757207 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Programmable logic array integrated circuit incorporating a first-in first-out memory' [patent_app_type] => 1 [patent_app_number] => 8/643809 [patent_app_country] => US [patent_app_date] => 1996-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8855 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757207.pdf [firstpage_image] =>[orig_patent_app_number] => 643809 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/643809
Programmable logic array integrated circuit incorporating a first-in first-out memory May 5, 1996 Issued
Array ( [id] => 3819068 [patent_doc_number] => 05710516 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-20 [patent_title] => 'Input logic signal buffer circuits' [patent_app_type] => 1 [patent_app_number] => 8/639922 [patent_app_country] => US [patent_app_date] => 1996-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2503 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/710/05710516.pdf [firstpage_image] =>[orig_patent_app_number] => 639922 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/639922
Input logic signal buffer circuits Apr 23, 1996 Issued
Array ( [id] => 3837737 [patent_doc_number] => 05712577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Anti-fuse programming circuit for user programmable integrated' [patent_app_type] => 1 [patent_app_number] => 8/634702 [patent_app_country] => US [patent_app_date] => 1996-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4757 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712577.pdf [firstpage_image] =>[orig_patent_app_number] => 634702 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/634702
Anti-fuse programming circuit for user programmable integrated Apr 17, 1996 Issued
Array ( [id] => 3749874 [patent_doc_number] => 05801548 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Configurable performance-optimized programmable logic device' [patent_app_type] => 1 [patent_app_number] => 8/630321 [patent_app_country] => US [patent_app_date] => 1996-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5793 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801548.pdf [firstpage_image] =>[orig_patent_app_number] => 630321 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/630321
Configurable performance-optimized programmable logic device Apr 10, 1996 Issued
Array ( [id] => 3734379 [patent_doc_number] => 05703499 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Address bit latching input circuit' [patent_app_type] => 1 [patent_app_number] => 8/630312 [patent_app_country] => US [patent_app_date] => 1996-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2739 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/703/05703499.pdf [firstpage_image] =>[orig_patent_app_number] => 630312 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/630312
Address bit latching input circuit Apr 9, 1996 Issued
Array ( [id] => 3737393 [patent_doc_number] => 05666070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Low power, high speed level shifter' [patent_app_type] => 1 [patent_app_number] => 8/629503 [patent_app_country] => US [patent_app_date] => 1996-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 2796 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/666/05666070.pdf [firstpage_image] =>[orig_patent_app_number] => 629503 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/629503
Low power, high speed level shifter Apr 8, 1996 Issued
Array ( [id] => 3893163 [patent_doc_number] => 05714892 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Three state logic input' [patent_app_type] => 1 [patent_app_number] => 8/627504 [patent_app_country] => US [patent_app_date] => 1996-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6906 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/714/05714892.pdf [firstpage_image] =>[orig_patent_app_number] => 627504 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/627504
Three state logic input Apr 3, 1996 Issued
Array ( [id] => 3884569 [patent_doc_number] => 05804988 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Logic and level conversion circuit' [patent_app_type] => 1 [patent_app_number] => 8/626608 [patent_app_country] => US [patent_app_date] => 1996-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4239 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/804/05804988.pdf [firstpage_image] =>[orig_patent_app_number] => 626608 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/626608
Logic and level conversion circuit Apr 1, 1996 Issued
Array ( [id] => 3737419 [patent_doc_number] => 05694056 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Fast pipeline frame full detector' [patent_app_type] => 1 [patent_app_number] => 8/627815 [patent_app_country] => US [patent_app_date] => 1996-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3747 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694056.pdf [firstpage_image] =>[orig_patent_app_number] => 627815 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/627815
Fast pipeline frame full detector Mar 31, 1996 Issued
Array ( [id] => 3699909 [patent_doc_number] => 05680062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Gunn transceiver logic input circuit for use in a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/625112 [patent_app_country] => US [patent_app_date] => 1996-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3868 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680062.pdf [firstpage_image] =>[orig_patent_app_number] => 625112 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/625112
Gunn transceiver logic input circuit for use in a semiconductor memory device Mar 31, 1996 Issued
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