Search

David R. Hudspeth

Supervisory Patent Examiner (ID: 5710, Phone: (571)272-7843 , Office: P/2657 )

Most Active Art Unit
2504
Art Unit(s)
2509, 2626, 2641, 2504, 2657, 2681, 2651, 2741
Total Applications
1592
Issued Applications
1465
Pending Applications
21
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3801211 [patent_doc_number] => 05781026 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'CMOS level shifter with steady-state and transient drivers' [patent_app_type] => 1 [patent_app_number] => 8/623310 [patent_app_country] => US [patent_app_date] => 1996-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 12876 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 409 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781026.pdf [firstpage_image] =>[orig_patent_app_number] => 623310 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/623310
CMOS level shifter with steady-state and transient drivers Mar 27, 1996 Issued
Array ( [id] => 3654168 [patent_doc_number] => 05684413 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Condensed single block PLA plus PAL architecture' [patent_app_type] => 1 [patent_app_number] => 8/623622 [patent_app_country] => US [patent_app_date] => 1996-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1171 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/684/05684413.pdf [firstpage_image] =>[orig_patent_app_number] => 623622 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/623622
Condensed single block PLA plus PAL architecture Mar 27, 1996 Issued
Array ( [id] => 3730877 [patent_doc_number] => 05701094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Logic circuits for wave pipelining' [patent_app_type] => 1 [patent_app_number] => 8/620466 [patent_app_country] => US [patent_app_date] => 1996-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 32 [patent_no_of_words] => 12266 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/701/05701094.pdf [firstpage_image] =>[orig_patent_app_number] => 620466 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/620466
Logic circuits for wave pipelining Mar 21, 1996 Issued
Array ( [id] => 3737488 [patent_doc_number] => 05694061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Semiconductor device having same conductive type MIS transistors, a simple circuit design, and a high productivity' [patent_app_type] => 1 [patent_app_number] => 8/621112 [patent_app_country] => US [patent_app_date] => 1996-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 77 [patent_no_of_words] => 13969 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694061.pdf [firstpage_image] =>[orig_patent_app_number] => 621112 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/621112
Semiconductor device having same conductive type MIS transistors, a simple circuit design, and a high productivity Mar 21, 1996 Issued
Array ( [id] => 3655351 [patent_doc_number] => 05606265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Semiconductor integrated circuits with power reduction mechanism' [patent_app_type] => 1 [patent_app_number] => 8/620686 [patent_app_country] => US [patent_app_date] => 1996-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 15378 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/606/05606265.pdf [firstpage_image] =>[orig_patent_app_number] => 620686 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/620686
Semiconductor integrated circuits with power reduction mechanism Mar 20, 1996 Issued
Array ( [id] => 3693448 [patent_doc_number] => 05644255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Circuits systems and methods for reducing power loss during transfer of data across a conductive line' [patent_app_type] => 1 [patent_app_number] => 8/620115 [patent_app_country] => US [patent_app_date] => 1996-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4440 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/644/05644255.pdf [firstpage_image] =>[orig_patent_app_number] => 620115 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/620115
Circuits systems and methods for reducing power loss during transfer of data across a conductive line Mar 20, 1996 Issued
Array ( [id] => 3730861 [patent_doc_number] => 05701093 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Adiabatic MOS logic and power supplying method and apparatus' [patent_app_type] => 1 [patent_app_number] => 8/616811 [patent_app_country] => US [patent_app_date] => 1996-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5958 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/701/05701093.pdf [firstpage_image] =>[orig_patent_app_number] => 616811 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/616811
Adiabatic MOS logic and power supplying method and apparatus Mar 14, 1996 Issued
Array ( [id] => 3670036 [patent_doc_number] => 05668482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'Bus maintenance circuit' [patent_app_type] => 1 [patent_app_number] => 8/616410 [patent_app_country] => US [patent_app_date] => 1996-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 7 [patent_no_of_words] => 3302 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668482.pdf [firstpage_image] =>[orig_patent_app_number] => 616410 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/616410
Bus maintenance circuit Mar 14, 1996 Issued
Array ( [id] => 3699912 [patent_doc_number] => 05661418 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Signal generation decoder circuit and method' [patent_app_type] => 1 [patent_app_number] => 8/615718 [patent_app_country] => US [patent_app_date] => 1996-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3394 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661418.pdf [firstpage_image] =>[orig_patent_app_number] => 615718 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/615718
Signal generation decoder circuit and method Mar 12, 1996 Issued
Array ( [id] => 3693408 [patent_doc_number] => 05644252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Driver for interfacing integrated circuits to transmission lines' [patent_app_type] => 1 [patent_app_number] => 8/613409 [patent_app_country] => US [patent_app_date] => 1996-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3624 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/644/05644252.pdf [firstpage_image] =>[orig_patent_app_number] => 613409 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/613409
Driver for interfacing integrated circuits to transmission lines Mar 10, 1996 Issued
Array ( [id] => 3693420 [patent_doc_number] => 05644253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Multiple-valued logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/618420 [patent_app_country] => US [patent_app_date] => 1996-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 49 [patent_no_of_words] => 11826 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/644/05644253.pdf [firstpage_image] =>[orig_patent_app_number] => 618420 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/618420
Multiple-valued logic circuit Mar 7, 1996 Issued
Array ( [id] => 3699875 [patent_doc_number] => 05661415 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Output buffer circuit with logic gate control circuitry' [patent_app_type] => 1 [patent_app_number] => 8/608318 [patent_app_country] => US [patent_app_date] => 1996-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 2878 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661415.pdf [firstpage_image] =>[orig_patent_app_number] => 608318 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/608318
Output buffer circuit with logic gate control circuitry Feb 27, 1996 Issued
Array ( [id] => 3822977 [patent_doc_number] => 05789945 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Method and circuit for improving metastable resolving time in low-power multi-state devices' [patent_app_type] => 1 [patent_app_number] => 8/607404 [patent_app_country] => US [patent_app_date] => 1996-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2031 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/789/05789945.pdf [firstpage_image] =>[orig_patent_app_number] => 607404 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/607404
Method and circuit for improving metastable resolving time in low-power multi-state devices Feb 26, 1996 Issued
Array ( [id] => 3737405 [patent_doc_number] => 05694055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Zero static power programmable logic cell' [patent_app_type] => 1 [patent_app_number] => 8/607405 [patent_app_country] => US [patent_app_date] => 1996-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1847 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 364 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694055.pdf [firstpage_image] =>[orig_patent_app_number] => 607405 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/607405
Zero static power programmable logic cell Feb 26, 1996 Issued
Array ( [id] => 3669870 [patent_doc_number] => 05598108 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'High-density erasable programmable logic device architecture using multiplexer interconnections, and registered macrocell with product term allocation and adjacent product term stealing' [patent_app_type] => 1 [patent_app_number] => 8/605445 [patent_app_country] => US [patent_app_date] => 1996-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 8827 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598108.pdf [firstpage_image] =>[orig_patent_app_number] => 605445 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/605445
High-density erasable programmable logic device architecture using multiplexer interconnections, and registered macrocell with product term allocation and adjacent product term stealing Feb 25, 1996 Issued
Array ( [id] => 3661081 [patent_doc_number] => 05623217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Field programmable gate array with write-port enabled memory' [patent_app_type] => 1 [patent_app_number] => 8/606702 [patent_app_country] => US [patent_app_date] => 1996-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1722 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623217.pdf [firstpage_image] =>[orig_patent_app_number] => 606702 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/606702
Field programmable gate array with write-port enabled memory Feb 25, 1996 Issued
Array ( [id] => 3707510 [patent_doc_number] => 05646550 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'High reliability output buffer for multiple voltage system' [patent_app_type] => 1 [patent_app_number] => 8/605422 [patent_app_country] => US [patent_app_date] => 1996-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6629 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646550.pdf [firstpage_image] =>[orig_patent_app_number] => 605422 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/605422
High reliability output buffer for multiple voltage system Feb 21, 1996 Issued
Array ( [id] => 3700577 [patent_doc_number] => 05619146 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-08 [patent_title] => 'Switching speed fluctuation detecting apparatus for logic circuit arrangement' [patent_app_type] => 1 [patent_app_number] => 8/604621 [patent_app_country] => US [patent_app_date] => 1996-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 66 [patent_no_of_words] => 5072 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/619/05619146.pdf [firstpage_image] =>[orig_patent_app_number] => 604621 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/604621
Switching speed fluctuation detecting apparatus for logic circuit arrangement Feb 20, 1996 Issued
Array ( [id] => 3729496 [patent_doc_number] => 05672983 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'Low noise output buffer circuit' [patent_app_type] => 1 [patent_app_number] => 8/604703 [patent_app_country] => US [patent_app_date] => 1996-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 6626 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/672/05672983.pdf [firstpage_image] =>[orig_patent_app_number] => 604703 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/604703
Low noise output buffer circuit Feb 20, 1996 Issued
Array ( [id] => 3707482 [patent_doc_number] => 05646548 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Efficient method and resulting structure for integrated circuits with flexible I/O interface and power supply voltages' [patent_app_type] => 1 [patent_app_number] => 8/601375 [patent_app_country] => US [patent_app_date] => 1996-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 10442 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646548.pdf [firstpage_image] =>[orig_patent_app_number] => 601375 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/601375
Efficient method and resulting structure for integrated circuits with flexible I/O interface and power supply voltages Feb 13, 1996 Issued
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