Search

David R. Hudspeth

Supervisory Patent Examiner (ID: 5710, Phone: (571)272-7843 , Office: P/2657 )

Most Active Art Unit
2504
Art Unit(s)
2509, 2626, 2641, 2504, 2657, 2681, 2651, 2741
Total Applications
1592
Issued Applications
1465
Pending Applications
21
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3663402 [patent_doc_number] => 05627480 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-06 [patent_title] => 'Tristatable bidirectional buffer for tristate bus lines' [patent_app_type] => 1 [patent_app_number] => 8/598308 [patent_app_country] => US [patent_app_date] => 1996-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4352 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/627/05627480.pdf [firstpage_image] =>[orig_patent_app_number] => 598308 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/598308
Tristatable bidirectional buffer for tristate bus lines Feb 7, 1996 Issued
Array ( [id] => 3667925 [patent_doc_number] => 05625302 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Address buffer for synchronous system' [patent_app_type] => 1 [patent_app_number] => 8/598304 [patent_app_country] => US [patent_app_date] => 1996-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1266 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/625/05625302.pdf [firstpage_image] =>[orig_patent_app_number] => 598304 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/598304
Address buffer for synchronous system Feb 7, 1996 Issued
Array ( [id] => 3736549 [patent_doc_number] => 05635851 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'Read and writable data bus particularly for programmable logic devices' [patent_app_type] => 1 [patent_app_number] => 8/595608 [patent_app_country] => US [patent_app_date] => 1996-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5180 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/635/05635851.pdf [firstpage_image] =>[orig_patent_app_number] => 595608 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/595608
Read and writable data bus particularly for programmable logic devices Feb 1, 1996 Issued
Array ( [id] => 3654182 [patent_doc_number] => 05684414 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Voltage level interface circuit with separate reference signal input and folded cascode structure' [patent_app_type] => 1 [patent_app_number] => 8/594618 [patent_app_country] => US [patent_app_date] => 1996-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2277 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/684/05684414.pdf [firstpage_image] =>[orig_patent_app_number] => 594618 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/594618
Voltage level interface circuit with separate reference signal input and folded cascode structure Feb 1, 1996 Issued
Array ( [id] => 3693434 [patent_doc_number] => 05644254 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Rapid switching input-output couplers for high rate data transfer buses' [patent_app_type] => 1 [patent_app_number] => 8/595003 [patent_app_country] => US [patent_app_date] => 1996-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6861 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/644/05644254.pdf [firstpage_image] =>[orig_patent_app_number] => 595003 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/595003
Rapid switching input-output couplers for high rate data transfer buses Jan 30, 1996 Issued
Array ( [id] => 3695348 [patent_doc_number] => 05604449 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Dual I/O logic for high voltage CMOS circuit using low voltage CMOS processes' [patent_app_type] => 1 [patent_app_number] => 8/592920 [patent_app_country] => US [patent_app_date] => 1996-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5886 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 533 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604449.pdf [firstpage_image] =>[orig_patent_app_number] => 592920 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/592920
Dual I/O logic for high voltage CMOS circuit using low voltage CMOS processes Jan 28, 1996 Issued
Array ( [id] => 3831659 [patent_doc_number] => 05731716 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Programmable multibit register for coincidence and jump operations and coincidence fuse cell' [patent_app_type] => 1 [patent_app_number] => 8/592122 [patent_app_country] => US [patent_app_date] => 1996-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 5154 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/731/05731716.pdf [firstpage_image] =>[orig_patent_app_number] => 592122 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/592122
Programmable multibit register for coincidence and jump operations and coincidence fuse cell Jan 25, 1996 Issued
Array ( [id] => 3666619 [patent_doc_number] => 05656946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Mode-selectable voltage driving circuit for use in semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/590301 [patent_app_country] => US [patent_app_date] => 1996-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2258 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/656/05656946.pdf [firstpage_image] =>[orig_patent_app_number] => 590301 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/590301
Mode-selectable voltage driving circuit for use in semiconductor memory device Jan 22, 1996 Issued
Array ( [id] => 3884824 [patent_doc_number] => 05748012 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Methodology to test pulsed logic circuits in pseudo-static mode' [patent_app_type] => 1 [patent_app_number] => 8/583300 [patent_app_country] => US [patent_app_date] => 1996-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1820 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748012.pdf [firstpage_image] =>[orig_patent_app_number] => 583300 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/583300
Methodology to test pulsed logic circuits in pseudo-static mode Jan 4, 1996 Issued
Array ( [id] => 3625910 [patent_doc_number] => 05614843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'CMOS-PECL level conversion circuit' [patent_app_type] => 1 [patent_app_number] => 8/583510 [patent_app_country] => US [patent_app_date] => 1996-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6234 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/614/05614843.pdf [firstpage_image] =>[orig_patent_app_number] => 583510 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/583510
CMOS-PECL level conversion circuit Jan 4, 1996 Issued
Array ( [id] => 3699817 [patent_doc_number] => 05661411 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Feedback controlled load logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/583812 [patent_app_country] => US [patent_app_date] => 1996-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4968 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661411.pdf [firstpage_image] =>[orig_patent_app_number] => 583812 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/583812
Feedback controlled load logic circuit Jan 4, 1996 Issued
08/583209 BIDIRECTIONAL VOLTAGE TRANSLATOR Jan 2, 1996 Abandoned
Array ( [id] => 3736712 [patent_doc_number] => 05635862 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'High-speed block id encoder circuit using dynamic logic' [patent_app_type] => 1 [patent_app_number] => 8/580656 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5126 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/635/05635862.pdf [firstpage_image] =>[orig_patent_app_number] => 580656 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/580656
High-speed block id encoder circuit using dynamic logic Dec 28, 1995 Issued
Array ( [id] => 3736681 [patent_doc_number] => 05635860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'Overvoltage-tolerant self-biasing CMOS output buffer' [patent_app_type] => 1 [patent_app_number] => 8/580413 [patent_app_country] => US [patent_app_date] => 1995-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3680 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/635/05635860.pdf [firstpage_image] =>[orig_patent_app_number] => 580413 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/580413
Overvoltage-tolerant self-biasing CMOS output buffer Dec 27, 1995 Issued
Array ( [id] => 3837752 [patent_doc_number] => 05712578 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'PLA architecture having improved clock signal to output timing using a type-I domino and plane' [patent_app_type] => 1 [patent_app_number] => 8/579095 [patent_app_country] => US [patent_app_date] => 1995-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5154 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712578.pdf [firstpage_image] =>[orig_patent_app_number] => 579095 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/579095
PLA architecture having improved clock signal to output timing using a type-I domino and plane Dec 26, 1995 Issued
Array ( [id] => 3654196 [patent_doc_number] => 05684415 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => '5 volt driver in a 3 volt CMOS process' [patent_app_type] => 1 [patent_app_number] => 8/575793 [patent_app_country] => US [patent_app_date] => 1995-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4099 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/684/05684415.pdf [firstpage_image] =>[orig_patent_app_number] => 575793 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/575793
5 volt driver in a 3 volt CMOS process Dec 21, 1995 Issued
Array ( [id] => 3673412 [patent_doc_number] => 05600265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Programmable interconnect architecture' [patent_app_type] => 1 [patent_app_number] => 8/575519 [patent_app_country] => US [patent_app_date] => 1995-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 4791 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/600/05600265.pdf [firstpage_image] =>[orig_patent_app_number] => 575519 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/575519
Programmable interconnect architecture Dec 19, 1995 Issued
Array ( [id] => 3629090 [patent_doc_number] => 05602497 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Precharged adiabatic pipelined logic' [patent_app_type] => 1 [patent_app_number] => 8/575934 [patent_app_country] => US [patent_app_date] => 1995-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7215 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/602/05602497.pdf [firstpage_image] =>[orig_patent_app_number] => 575934 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/575934
Precharged adiabatic pipelined logic Dec 19, 1995 Issued
Array ( [id] => 3628638 [patent_doc_number] => 05612630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'Asynchronous self-adjusting input circuit' [patent_app_type] => 1 [patent_app_number] => 8/548801 [patent_app_country] => US [patent_app_date] => 1995-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7135 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/612/05612630.pdf [firstpage_image] =>[orig_patent_app_number] => 548801 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/548801
Asynchronous self-adjusting input circuit Dec 18, 1995 Issued
Array ( [id] => 3699882 [patent_doc_number] => 05680060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Method of and circuit arrangement for terminating a line connected to a CMOS integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/574550 [patent_app_country] => US [patent_app_date] => 1995-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3787 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680060.pdf [firstpage_image] =>[orig_patent_app_number] => 574550 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/574550
Method of and circuit arrangement for terminating a line connected to a CMOS integrated circuit Dec 18, 1995 Issued
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