
David R. Hudspeth
Supervisory Patent Examiner (ID: 5710, Phone: (571)272-7843 , Office: P/2657 )
| Most Active Art Unit | 2504 |
| Art Unit(s) | 2509, 2626, 2641, 2504, 2657, 2681, 2651, 2741 |
| Total Applications | 1592 |
| Issued Applications | 1465 |
| Pending Applications | 21 |
| Abandoned Applications | 105 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3663402
[patent_doc_number] => 05627480
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-06
[patent_title] => 'Tristatable bidirectional buffer for tristate bus lines'
[patent_app_type] => 1
[patent_app_number] => 8/598308
[patent_app_country] => US
[patent_app_date] => 1996-02-08
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[pdf_file] => patents/05/627/05627480.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/598308 | Tristatable bidirectional buffer for tristate bus lines | Feb 7, 1996 | Issued |
Array
(
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[patent_doc_number] => 05625302
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[patent_issue_date] => 1997-04-29
[patent_title] => 'Address buffer for synchronous system'
[patent_app_type] => 1
[patent_app_number] => 8/598304
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Array
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[patent_issue_date] => 1997-06-03
[patent_title] => 'Read and writable data bus particularly for programmable logic devices'
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[patent_app_number] => 8/595608
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/595608 | Read and writable data bus particularly for programmable logic devices | Feb 1, 1996 | Issued |
Array
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[patent_doc_number] => 05684414
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[patent_issue_date] => 1997-11-04
[patent_title] => 'Voltage level interface circuit with separate reference signal input and folded cascode structure'
[patent_app_type] => 1
[patent_app_number] => 8/594618
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[patent_app_date] => 1996-02-02
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[firstpage_image] =>[orig_patent_app_number] => 594618
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/594618 | Voltage level interface circuit with separate reference signal input and folded cascode structure | Feb 1, 1996 | Issued |
Array
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[id] => 3693434
[patent_doc_number] => 05644254
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[patent_issue_date] => 1997-07-01
[patent_title] => 'Rapid switching input-output couplers for high rate data transfer buses'
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[patent_app_number] => 8/595003
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/595003 | Rapid switching input-output couplers for high rate data transfer buses | Jan 30, 1996 | Issued |
Array
(
[id] => 3695348
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[patent_issue_date] => 1997-02-18
[patent_title] => 'Dual I/O logic for high voltage CMOS circuit using low voltage CMOS processes'
[patent_app_type] => 1
[patent_app_number] => 8/592920
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/592920 | Dual I/O logic for high voltage CMOS circuit using low voltage CMOS processes | Jan 28, 1996 | Issued |
Array
(
[id] => 3831659
[patent_doc_number] => 05731716
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[patent_issue_date] => 1998-03-24
[patent_title] => 'Programmable multibit register for coincidence and jump operations and coincidence fuse cell'
[patent_app_type] => 1
[patent_app_number] => 8/592122
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/592122 | Programmable multibit register for coincidence and jump operations and coincidence fuse cell | Jan 25, 1996 | Issued |
Array
(
[id] => 3666619
[patent_doc_number] => 05656946
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[patent_kind] => NA
[patent_issue_date] => 1997-08-12
[patent_title] => 'Mode-selectable voltage driving circuit for use in semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/590301
[patent_app_country] => US
[patent_app_date] => 1996-01-23
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/590301 | Mode-selectable voltage driving circuit for use in semiconductor memory device | Jan 22, 1996 | Issued |
Array
(
[id] => 3884824
[patent_doc_number] => 05748012
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[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Methodology to test pulsed logic circuits in pseudo-static mode'
[patent_app_type] => 1
[patent_app_number] => 8/583300
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/583300 | Methodology to test pulsed logic circuits in pseudo-static mode | Jan 4, 1996 | Issued |
Array
(
[id] => 3625910
[patent_doc_number] => 05614843
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[patent_kind] => NA
[patent_issue_date] => 1997-03-25
[patent_title] => 'CMOS-PECL level conversion circuit'
[patent_app_type] => 1
[patent_app_number] => 8/583510
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 583510
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/583510 | CMOS-PECL level conversion circuit | Jan 4, 1996 | Issued |
Array
(
[id] => 3699817
[patent_doc_number] => 05661411
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-26
[patent_title] => 'Feedback controlled load logic circuit'
[patent_app_type] => 1
[patent_app_number] => 8/583812
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[firstpage_image] =>[orig_patent_app_number] => 583812
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/583812 | Feedback controlled load logic circuit | Jan 4, 1996 | Issued |
| 08/583209 | BIDIRECTIONAL VOLTAGE TRANSLATOR | Jan 2, 1996 | Abandoned |
Array
(
[id] => 3736712
[patent_doc_number] => 05635862
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[patent_title] => 'High-speed block id encoder circuit using dynamic logic'
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[patent_app_number] => 8/580656
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/580656 | High-speed block id encoder circuit using dynamic logic | Dec 28, 1995 | Issued |
Array
(
[id] => 3736681
[patent_doc_number] => 05635860
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[patent_title] => 'Overvoltage-tolerant self-biasing CMOS output buffer'
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Array
(
[id] => 3837752
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[patent_title] => 'PLA architecture having improved clock signal to output timing using a type-I domino and plane'
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Array
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Array
(
[id] => 3673412
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[firstpage_image] =>[orig_patent_app_number] => 575519
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/575519 | Programmable interconnect architecture | Dec 19, 1995 | Issued |
Array
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Array
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[firstpage_image] =>[orig_patent_app_number] => 574550
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/574550 | Method of and circuit arrangement for terminating a line connected to a CMOS integrated circuit | Dec 18, 1995 | Issued |