David R. Hudspeth

Array ( [id] => 3514665 [patent_doc_number] => 05587667 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'Output buffer circuit for high-speed logic operation' [patent_app_type] => 1 [patent_app_number] => 8/575118 [patent_app_country] => US [patent_app_date] => 1995-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/587/05587667.pdf [firstpage_image] =>[orig_patent_app_number] => 575118 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3694205 [patent_doc_number] => 05663662 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Library group and semiconductor integrated circuit structured thereof' [patent_app_type] => 1 [patent_app_number] => 8/574378 [patent_app_country] => US [patent_app_date] => 1995-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 4850 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/663/05663662.pdf [firstpage_image] =>[orig_patent_app_number] => 574378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3627114 [patent_doc_number] => 05689198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Circuitry and method for gating information' [patent_app_type] => 1 [patent_app_number] => 8/574085 [patent_app_country] => US [patent_app_date] => 1995-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3718 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/689/05689198.pdf [firstpage_image] =>[orig_patent_app_number] => 574085 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3693704 [patent_doc_number] => 05691654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Voltage level translator circuit' [patent_app_type] => 1 [patent_app_number] => 8/572618 [patent_app_country] => US [patent_app_date] => 1995-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4242 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/691/05691654.pdf [firstpage_image] =>[orig_patent_app_number] => 572618 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3668163 [patent_doc_number] => 05627797 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-06 [patent_title] => 'Full and empty flag generator for synchronous FIFOS' [patent_app_type] => 1 [patent_app_number] => 8/572623 [patent_app_country] => US [patent_app_date] => 1995-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3447 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/627/05627797.pdf [firstpage_image] =>[orig_patent_app_number] => 572623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3664444 [patent_doc_number] => 05592104 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Output buffer having transmission gate and isolated supply terminals' [patent_app_type] => 1 [patent_app_number] => 8/571724 [patent_app_country] => US [patent_app_date] => 1995-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3618 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/592/05592104.pdf [firstpage_image] =>[orig_patent_app_number] => 571724 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3699777 [patent_doc_number] => 05650734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Programming programmable transistor devices using state machines' [patent_app_type] => 1 [patent_app_number] => 8/570117 [patent_app_country] => US [patent_app_date] => 1995-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 5868 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/650/05650734.pdf [firstpage_image] =>[orig_patent_app_number] => 570117 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3700804 [patent_doc_number] => 05596286 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Current limiting devices to reduce leakage, photo, or stand-by current in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/570368 [patent_app_country] => US [patent_app_date] => 1995-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3295 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596286.pdf [firstpage_image] =>[orig_patent_app_number] => 570368 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3627100 [patent_doc_number] => 05689197 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'BIMOS-type current switch apparatus' [patent_app_type] => 1 [patent_app_number] => 8/569691 [patent_app_country] => US [patent_app_date] => 1995-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 6157 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/689/05689197.pdf [firstpage_image] =>[orig_patent_app_number] => 569691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3716024 [patent_doc_number] => 05669684 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Logic level shifter with power on control' [patent_app_type] => 1 [patent_app_number] => 8/570170 [patent_app_country] => US [patent_app_date] => 1995-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2362 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/669/05669684.pdf [firstpage_image] =>[orig_patent_app_number] => 570170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3639622 [patent_doc_number] => 05631581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-20 [patent_title] => 'Microelectronic integrated circuit including triangular semiconductor \"and\" gate device' [patent_app_type] => 1 [patent_app_number] => 8/567952 [patent_app_country] => US [patent_app_date] => 1995-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 4909 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/631/05631581.pdf [firstpage_image] =>[orig_patent_app_number] => 567952 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3627086 [patent_doc_number] => 05689196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Circuit comprising a data communication bus' [patent_app_type] => 1 [patent_app_number] => 8/565774 [patent_app_country] => US [patent_app_date] => 1995-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4331 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/689/05689196.pdf [firstpage_image] =>[orig_patent_app_number] => 565774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3707594 [patent_doc_number] => 05646556 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Apparatus and method for precharging bus conductors to minimize both drive delay and crosstalk within the bus' [patent_app_type] => 1 [patent_app_number] => 8/562805 [patent_app_country] => US [patent_app_date] => 1995-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4255 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646556.pdf [firstpage_image] =>[orig_patent_app_number] => 562805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3512451 [patent_doc_number] => 05570038 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-29 [patent_title] => 'Semiconductor integrated circuit device with data output circuit' [patent_app_type] => 1 [patent_app_number] => 8/561064 [patent_app_country] => US [patent_app_date] => 1995-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 10582 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 27 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/570/05570038.pdf [firstpage_image] =>[orig_patent_app_number] => 561064 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3514750 [patent_doc_number] => 05587673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'Clock frequency multiplying and squaring circuit and method' [patent_app_type] => 1 [patent_app_number] => 8/562228 [patent_app_country] => US [patent_app_date] => 1995-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2213 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/587/05587673.pdf [firstpage_image] =>[orig_patent_app_number] => 562228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3734290 [patent_doc_number] => 05670898 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Low-power, compact digital logic topology that facilitates large fan-in and high-speed circuit performance' [patent_app_type] => 1 [patent_app_number] => 8/561914 [patent_app_country] => US [patent_app_date] => 1995-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 4171 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/670/05670898.pdf [firstpage_image] =>[orig_patent_app_number] => 561914 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3736580 [patent_doc_number] => 05635853 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'Inherently balanced voltage regulation and current supply for bus termination' [patent_app_type] => 1 [patent_app_number] => 8/556723 [patent_app_country] => US [patent_app_date] => 1995-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2838 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/635/05635853.pdf [firstpage_image] =>[orig_patent_app_number] => 556723 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3666696 [patent_doc_number] => 05656952 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'All-MOS differential high speed output driver for providing positive-ECL levels into a variable load impedance' [patent_app_type] => 1 [patent_app_number] => 8/558010 [patent_app_country] => US [patent_app_date] => 1995-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4574 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/656/05656952.pdf [firstpage_image] =>[orig_patent_app_number] => 558010 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3653216 [patent_doc_number] => 05638008 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-10 [patent_title] => 'Method and apparatus for generating an asynchronously clocked signal in a synchronously clocked programmable device' [patent_app_type] => 1 [patent_app_number] => 8/550165 [patent_app_country] => US [patent_app_date] => 1995-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7294 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/638/05638008.pdf [firstpage_image] =>[orig_patent_app_number] => 550165 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3885007 [patent_doc_number] => 05729152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Termination circuits for reduced swing signal lines and methods for operating same' [patent_app_type] => 1 [patent_app_number] => 8/549610 [patent_app_country] => US [patent_app_date] => 1995-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 27 [patent_no_of_words] => 17011 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/729/05729152.pdf [firstpage_image] =>[orig_patent_app_number] => 549610 [rel_patent_id] =>[rel_patent_doc_number] =>)