Search

David R. Hudspeth

Supervisory Patent Examiner (ID: 5710, Phone: (571)272-7843 , Office: P/2657 )

Most Active Art Unit
2504
Art Unit(s)
2509, 2626, 2641, 2504, 2657, 2681, 2651, 2741
Total Applications
1592
Issued Applications
1465
Pending Applications
21
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3655402 [patent_doc_number] => 05606269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Non-delay based address transition detector (ATD)' [patent_app_type] => 1 [patent_app_number] => 8/548651 [patent_app_country] => US [patent_app_date] => 1995-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2692 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/606/05606269.pdf [firstpage_image] =>[orig_patent_app_number] => 548651 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/548651
Non-delay based address transition detector (ATD) Oct 25, 1995 Issued
Array ( [id] => 3629036 [patent_doc_number] => 05602493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Bias circuit for an input terminal' [patent_app_type] => 1 [patent_app_number] => 8/548060 [patent_app_country] => US [patent_app_date] => 1995-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4533 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/602/05602493.pdf [firstpage_image] =>[orig_patent_app_number] => 548060 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/548060
Bias circuit for an input terminal Oct 24, 1995 Issued
Array ( [id] => 3654174 [patent_doc_number] => 05640107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Method for in-circuit programming of a field-programmable gate array configuration memory' [patent_app_type] => 1 [patent_app_number] => 8/547351 [patent_app_country] => US [patent_app_date] => 1995-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5501 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/640/05640107.pdf [firstpage_image] =>[orig_patent_app_number] => 547351 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/547351
Method for in-circuit programming of a field-programmable gate array configuration memory Oct 23, 1995 Issued
Array ( [id] => 3630231 [patent_doc_number] => 05608342 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-04 [patent_title] => 'Hierarchical programming of electrically configurable integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/546756 [patent_app_country] => US [patent_app_date] => 1995-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4893 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/608/05608342.pdf [firstpage_image] =>[orig_patent_app_number] => 546756 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/546756
Hierarchical programming of electrically configurable integrated circuits Oct 22, 1995 Issued
Array ( [id] => 3673396 [patent_doc_number] => 05600264 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Programmable single buffered six pass transistor configuration' [patent_app_type] => 1 [patent_app_number] => 8/543454 [patent_app_country] => US [patent_app_date] => 1995-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3693 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/600/05600264.pdf [firstpage_image] =>[orig_patent_app_number] => 543454 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/543454
Programmable single buffered six pass transistor configuration Oct 15, 1995 Issued
Array ( [id] => 3628067 [patent_doc_number] => 05594367 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Output multiplexer within input/output circuit for time multiplexing and high speed logic' [patent_app_type] => 1 [patent_app_number] => 8/543521 [patent_app_country] => US [patent_app_date] => 1995-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 5912 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/594/05594367.pdf [firstpage_image] =>[orig_patent_app_number] => 543521 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/543521
Output multiplexer within input/output circuit for time multiplexing and high speed logic Oct 15, 1995 Issued
Array ( [id] => 3654140 [patent_doc_number] => 05684411 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Self-configuring bus' [patent_app_type] => 1 [patent_app_number] => 8/542763 [patent_app_country] => US [patent_app_date] => 1995-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4196 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/684/05684411.pdf [firstpage_image] =>[orig_patent_app_number] => 542763 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/542763
Self-configuring bus Oct 12, 1995 Issued
Array ( [id] => 3595440 [patent_doc_number] => 05585744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Circuits systems and methods for reducing power loss during transfer of data across a conductive line' [patent_app_type] => 1 [patent_app_number] => 8/543210 [patent_app_country] => US [patent_app_date] => 1995-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3970 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/585/05585744.pdf [firstpage_image] =>[orig_patent_app_number] => 543210 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/543210
Circuits systems and methods for reducing power loss during transfer of data across a conductive line Oct 12, 1995 Issued
Array ( [id] => 3627999 [patent_doc_number] => 05594362 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Gatable level-pulling circuit' [patent_app_type] => 1 [patent_app_number] => 8/543248 [patent_app_country] => US [patent_app_date] => 1995-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2497 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/594/05594362.pdf [firstpage_image] =>[orig_patent_app_number] => 543248 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/543248
Gatable level-pulling circuit Oct 12, 1995 Issued
Array ( [id] => 3736623 [patent_doc_number] => 05635856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'High speed programmable macrocell with combined path for storage and combinatorial modes' [patent_app_type] => 1 [patent_app_number] => 8/538519 [patent_app_country] => US [patent_app_date] => 1995-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5358 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/635/05635856.pdf [firstpage_image] =>[orig_patent_app_number] => 538519 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/538519
High speed programmable macrocell with combined path for storage and combinatorial modes Oct 2, 1995 Issued
Array ( [id] => 3593465 [patent_doc_number] => 05550489 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'Secondary clock source for low power, fast response clocking' [patent_app_type] => 1 [patent_app_number] => 8/536314 [patent_app_country] => US [patent_app_date] => 1995-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6491 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/550/05550489.pdf [firstpage_image] =>[orig_patent_app_number] => 536314 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/536314
Secondary clock source for low power, fast response clocking Sep 28, 1995 Issued
Array ( [id] => 3604137 [patent_doc_number] => 05559453 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Interlocked restore circuit' [patent_app_type] => 1 [patent_app_number] => 8/534920 [patent_app_country] => US [patent_app_date] => 1995-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2077 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559453.pdf [firstpage_image] =>[orig_patent_app_number] => 534920 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/534920
Interlocked restore circuit Sep 27, 1995 Issued
Array ( [id] => 3596054 [patent_doc_number] => 05568068 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Buffer circuit for regulating driving current' [patent_app_type] => 1 [patent_app_number] => 8/534114 [patent_app_country] => US [patent_app_date] => 1995-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 7309 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/568/05568068.pdf [firstpage_image] =>[orig_patent_app_number] => 534114 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/534114
Buffer circuit for regulating driving current Sep 25, 1995 Issued
Array ( [id] => 3617840 [patent_doc_number] => 05565796 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'Bus drive circuit, receiver circuit, and bus system' [patent_app_type] => 1 [patent_app_number] => 8/533722 [patent_app_country] => US [patent_app_date] => 1995-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 14228 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/565/05565796.pdf [firstpage_image] =>[orig_patent_app_number] => 533722 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/533722
Bus drive circuit, receiver circuit, and bus system Sep 25, 1995 Issued
Array ( [id] => 4021293 [patent_doc_number] => 05880600 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Device for interfacing logic signals from the LLL level to the TTL and CMOS level' [patent_app_type] => 1 [patent_app_number] => 8/533400 [patent_app_country] => US [patent_app_date] => 1995-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4070 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880600.pdf [firstpage_image] =>[orig_patent_app_number] => 533400 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/533400
Device for interfacing logic signals from the LLL level to the TTL and CMOS level Sep 24, 1995 Issued
Array ( [id] => 3790438 [patent_doc_number] => 05774841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Real-time reconfigurable adaptive speech recognition command and control apparatus and method' [patent_app_type] => 1 [patent_app_number] => 8/536302 [patent_app_country] => US [patent_app_date] => 1995-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11289 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774841.pdf [firstpage_image] =>[orig_patent_app_number] => 536302 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/536302
Real-time reconfigurable adaptive speech recognition command and control apparatus and method Sep 19, 1995 Issued
Array ( [id] => 3555729 [patent_doc_number] => 05572145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Method for minimizing ground bounce in digital circuits via time domain shifts' [patent_app_type] => 1 [patent_app_number] => 8/523923 [patent_app_country] => US [patent_app_date] => 1995-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2540 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/572/05572145.pdf [firstpage_image] =>[orig_patent_app_number] => 523923 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/523923
Method for minimizing ground bounce in digital circuits via time domain shifts Sep 5, 1995 Issued
Array ( [id] => 3695338 [patent_doc_number] => 05604448 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Output buffer circuit having low noise characteristics' [patent_app_type] => 1 [patent_app_number] => 8/523307 [patent_app_country] => US [patent_app_date] => 1995-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1831 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604448.pdf [firstpage_image] =>[orig_patent_app_number] => 523307 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/523307
Output buffer circuit having low noise characteristics Sep 4, 1995 Issued
Array ( [id] => 3655374 [patent_doc_number] => 05606267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Programmable logic module and architecture for field programmable gate array device' [patent_app_type] => 1 [patent_app_number] => 8/522945 [patent_app_country] => US [patent_app_date] => 1995-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 11971 [patent_no_of_claims] => 81 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/606/05606267.pdf [firstpage_image] =>[orig_patent_app_number] => 522945 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/522945
Programmable logic module and architecture for field programmable gate array device Aug 31, 1995 Issued
Array ( [id] => 3663447 [patent_doc_number] => 05627483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-06 [patent_title] => 'Emitter coupled logic circuit with MOS differential stage' [patent_app_type] => 1 [patent_app_number] => 8/521518 [patent_app_country] => US [patent_app_date] => 1995-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2486 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/627/05627483.pdf [firstpage_image] =>[orig_patent_app_number] => 521518 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/521518
Emitter coupled logic circuit with MOS differential stage Aug 29, 1995 Issued
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