Search

David Robertson

Examiner (ID: 18617)

Most Active Art Unit
2121
Art Unit(s)
2163, 2127, 3623, 2121
Total Applications
304
Issued Applications
193
Pending Applications
23
Abandoned Applications
92

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18766765 [patent_doc_number] => 11817172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Table management method, memory storage device and memory control circuit unit [patent_app_type] => utility [patent_app_number] => 17/732532 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 8868 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17732532 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/732532
Table management method, memory storage device and memory control circuit unit Apr 28, 2022 Issued
Array ( [id] => 18743085 [patent_doc_number] => 20230352073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR CONFIGURABLE MEMORY [patent_app_type] => utility [patent_app_number] => 17/732885 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17732885 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/732885
Apparatuses, systems, and methods for configurable memory Apr 28, 2022 Issued
Array ( [id] => 18387070 [patent_doc_number] => 11657859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Memory device, controller controlling the same, memory system including the same, and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/732220 [patent_app_country] => US [patent_app_date] => 2022-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 8054 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17732220 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/732220
Memory device, controller controlling the same, memory system including the same, and operating method thereof Apr 27, 2022 Issued
Array ( [id] => 18743093 [patent_doc_number] => 20230352081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => LOOK AHEAD SWITCHING CIRCUIT FOR A MULTI-RANK SYSTEM [patent_app_type] => utility [patent_app_number] => 17/730379 [patent_app_country] => US [patent_app_date] => 2022-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10502 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17730379 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/730379
Look ahead switching circuit for a multi-rank system Apr 26, 2022 Issued
Array ( [id] => 20611023 [patent_doc_number] => 12586627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Refresh performance optimizations for DRAM technologies with sub-channel and/or pseudo-channel configurations [patent_app_type] => utility [patent_app_number] => 17/729433 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17729433 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/729433
Refresh performance optimizations for DRAM technologies with sub-channel and/or pseudo-channel configurations Apr 25, 2022 Issued
Array ( [id] => 19062906 [patent_doc_number] => 11942151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Current references for memory cells [patent_app_type] => utility [patent_app_number] => 17/720957 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8700 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17720957 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/720957
Current references for memory cells Apr 13, 2022 Issued
Array ( [id] => 18539795 [patent_doc_number] => 20230244903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => ARTIFICIAL NEURAL NETWORK COMPRISING AN ANALOG ARRAY AND A DIGITAL ARRAY [patent_app_type] => utility [patent_app_number] => 17/721254 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13775 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721254 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/721254
Artificial neural network comprising an analog array and a digital array Apr 13, 2022 Issued
Array ( [id] => 17778934 [patent_doc_number] => 20220245284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => COMPUTER-IMPLEMENTED METHOD FOR IMPROVING A SOCIAL NETWORK SITE COMPUTER NETWORK, AND TERMINAL, SYSTEM AND COMPUTER READABLE MEDIUM FOR THE SAME [patent_app_type] => utility [patent_app_number] => 17/718364 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 474 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718364 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718364
Computer-implemented method for improving a social network site computer network, and terminal, system and computer readable medium for the same Apr 11, 2022 Issued
Array ( [id] => 17809668 [patent_doc_number] => 20220261503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => COMPUTER-IMPLEMENTED METHOD FOR IMPROVING A SOCIAL NETWORK SITE COMUTER NETWORK, AND TERMINAL, SYSTEM AND COMPUTER READABLE MEDIUM FOR THE SAME [patent_app_type] => utility [patent_app_number] => 17/718312 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 472 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718312 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718312
COMPUTER-IMPLEMENTED METHOD FOR IMPROVING A SOCIAL NETWORK SITE COMUTER NETWORK, AND TERMINAL, SYSTEM AND COMPUTER READABLE MEDIUM FOR THE SAME Apr 10, 2022 Abandoned
Array ( [id] => 19029744 [patent_doc_number] => 11929107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Techniques for memory cell refresh [patent_app_type] => utility [patent_app_number] => 17/712972 [patent_app_country] => US [patent_app_date] => 2022-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10041 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712972 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/712972
Techniques for memory cell refresh Apr 3, 2022 Issued
Array ( [id] => 18983318 [patent_doc_number] => 11908503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Nonvolatile memory devices having enhanced write drivers therein [patent_app_type] => utility [patent_app_number] => 17/711297 [patent_app_country] => US [patent_app_date] => 2022-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11477 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17711297 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/711297
Nonvolatile memory devices having enhanced write drivers therein Mar 31, 2022 Issued
Array ( [id] => 17724427 [patent_doc_number] => 20220217149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => DYNAMIC AUTHORIZATION CONTROL SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 17/700322 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14885 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17700322 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/700322
Dynamic authorization control system and method Mar 20, 2022 Issued
Array ( [id] => 17708766 [patent_doc_number] => 20220208774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => MEMORY DEVICE AND MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/698929 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6884 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17698929 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/698929
Memory device and manufacturing method Mar 17, 2022 Issued
Array ( [id] => 18346692 [patent_doc_number] => 20230134802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => FERROELECTRIC MEMORY OPERATION BIAS AND POWER DOMAINS [patent_app_type] => utility [patent_app_number] => 17/696552 [patent_app_country] => US [patent_app_date] => 2022-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17696552 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/696552
Ferroelectric memory operation bias and power domains Mar 15, 2022 Issued
Array ( [id] => 18651870 [patent_doc_number] => 20230297706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => DETECTION AND MITIGATION OF HIGH-RISK ONLINE ACTIVITY IN A COMPUTING PLATFORM [patent_app_type] => utility [patent_app_number] => 17/695715 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695715 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695715
Detection and mitigation of high-risk online activity in a computing platform Mar 14, 2022 Issued
Array ( [id] => 19093689 [patent_doc_number] => 11955153 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-04-09 [patent_title] => Multi-element gain memory bit-cell having stacked and folded planar memory elements with and without offset [patent_app_type] => utility [patent_app_number] => 17/654908 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 85 [patent_no_of_words] => 71120 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654908 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654908
Multi-element gain memory bit-cell having stacked and folded planar memory elements with and without offset Mar 14, 2022 Issued
Array ( [id] => 18617715 [patent_doc_number] => 20230284456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => ONE TRANSISTOR AND N MEMORY ELEMENT BASED MEMORY BIT-CELL HAVING STACKED AND FOLDED PLANAR MEMORY ELEMENTS WITH AND WITHOUT OFFSET [patent_app_type] => utility [patent_app_number] => 17/654905 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 71040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654905 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654905
One transistor and N memory element based memory bit-cell having stacked and folded planar memory elements with and without offset Mar 14, 2022 Issued
Array ( [id] => 19640478 [patent_doc_number] => 12171103 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-12-17 [patent_title] => Multi-input threshold gate having stacked and folded non-planar capacitors [patent_app_type] => utility [patent_app_number] => 17/654764 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 85 [patent_no_of_words] => 71120 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654764 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654764
Multi-input threshold gate having stacked and folded non-planar capacitors Mar 13, 2022 Issued
Array ( [id] => 19153838 [patent_doc_number] => 11978762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-05-07 [patent_title] => Planar capacitors with non-linear polar material staggered on a shared electrode [patent_app_type] => utility [patent_app_number] => 17/654802 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 85 [patent_no_of_words] => 71114 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654802 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654802
Planar capacitors with non-linear polar material staggered on a shared electrode Mar 13, 2022 Issued
Array ( [id] => 17691866 [patent_doc_number] => 20220199159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => PCRAM ANALOG PROGRAMMING BY A GRADUAL RESET COOLING STEP [patent_app_type] => utility [patent_app_number] => 17/692548 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17692548 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/692548
PCRAM analog programming by a gradual reset cooling step Mar 10, 2022 Issued
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