
David Robertson
Examiner (ID: 18617)
| Most Active Art Unit | 2121 |
| Art Unit(s) | 2163, 2127, 3623, 2121 |
| Total Applications | 304 |
| Issued Applications | 193 |
| Pending Applications | 23 |
| Abandoned Applications | 92 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 15906249
[patent_doc_number] => 20200152645
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-14
[patent_title] => Memory Cell And An Array Of Memory Cells
[patent_app_type] => utility
[patent_app_number] => 16/743088
[patent_app_country] => US
[patent_app_date] => 2020-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4131
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16743088
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/743088 | Memory cell and an array of memory cells | Jan 14, 2020 | Issued |
Array
(
[id] => 16834970
[patent_doc_number] => 11011228
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-18
[patent_title] => Memory device having an increased sensing margin
[patent_app_type] => utility
[patent_app_number] => 16/741153
[patent_app_country] => US
[patent_app_date] => 2020-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 28
[patent_no_of_words] => 13150
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741153
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/741153 | Memory device having an increased sensing margin | Jan 12, 2020 | Issued |
Array
(
[id] => 15966663
[patent_doc_number] => 20200167083
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-28
[patent_title] => TECHNIQUES FOR CONTROLLING RECYCLING OF BLOCKS OF MEMORY
[patent_app_type] => utility
[patent_app_number] => 16/739294
[patent_app_country] => US
[patent_app_date] => 2020-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4508
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16739294
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/739294 | TECHNIQUES FOR CONTROLLING RECYCLING OF BLOCKS OF MEMORY | Jan 9, 2020 | Abandoned |
Array
(
[id] => 17396676
[patent_doc_number] => 11245704
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-08
[patent_title] => Automatically executing responsive actions based on a verification of an account lineage chain
[patent_app_type] => utility
[patent_app_number] => 16/737502
[patent_app_country] => US
[patent_app_date] => 2020-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 17117
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16737502
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/737502 | Automatically executing responsive actions based on a verification of an account lineage chain | Jan 7, 2020 | Issued |
Array
(
[id] => 16943963
[patent_doc_number] => 11056211
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-07-06
[patent_title] => Apparatus and method for handling temperature dependent failures in a memory device
[patent_app_type] => utility
[patent_app_number] => 16/737551
[patent_app_country] => US
[patent_app_date] => 2020-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 5469
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16737551
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/737551 | Apparatus and method for handling temperature dependent failures in a memory device | Jan 7, 2020 | Issued |
Array
(
[id] => 16951434
[patent_doc_number] => 20210210126
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-08
[patent_title] => TIMING CHAINS FOR ACCESSING MEMORY CELLS
[patent_app_type] => utility
[patent_app_number] => 16/737139
[patent_app_country] => US
[patent_app_date] => 2020-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12377
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16737139
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/737139 | Timing chains for accessing memory cells | Jan 7, 2020 | Issued |
Array
(
[id] => 16637761
[patent_doc_number] => 10916275
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-02-09
[patent_title] => Write driver and pre-charge circuitry for high performance pseudo-dual port (PDP) memories
[patent_app_type] => utility
[patent_app_number] => 16/735539
[patent_app_country] => US
[patent_app_date] => 2020-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10067
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16735539
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/735539 | Write driver and pre-charge circuitry for high performance pseudo-dual port (PDP) memories | Jan 5, 2020 | Issued |
Array
(
[id] => 16609050
[patent_doc_number] => 10910063
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-02
[patent_title] => Memory device and operating method thereof
[patent_app_type] => utility
[patent_app_number] => 16/732949
[patent_app_country] => US
[patent_app_date] => 2020-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 21
[patent_no_of_words] => 16440
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16732949
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/732949 | Memory device and operating method thereof | Jan 1, 2020 | Issued |
Array
(
[id] => 15839933
[patent_doc_number] => 20200135249
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-30
[patent_title] => APPARATUSES AND METHOD FOR REDUCING ROW ADDRESS TO COLUMN ADDRESS DELAY
[patent_app_type] => utility
[patent_app_number] => 16/729185
[patent_app_country] => US
[patent_app_date] => 2019-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8318
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16729185
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/729185 | Apparatuses and method for reducing row address to column address delay | Dec 26, 2019 | Issued |
Array
(
[id] => 16536247
[patent_doc_number] => 10878860
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-12-29
[patent_title] => Multi-level signaling scheme for memory interface
[patent_app_type] => utility
[patent_app_number] => 16/728451
[patent_app_country] => US
[patent_app_date] => 2019-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 6691
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16728451
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/728451 | Multi-level signaling scheme for memory interface | Dec 26, 2019 | Issued |
Array
(
[id] => 15836453
[patent_doc_number] => 20200133509
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-30
[patent_title] => MEMORY DEVICE INCLUDING MIXED NON-VOLATILE MEMORY CELL TYPES
[patent_app_type] => utility
[patent_app_number] => 16/727441
[patent_app_country] => US
[patent_app_date] => 2019-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15859
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727441
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/727441 | Memory device including mixed non-volatile memory cell types | Dec 25, 2019 | Issued |
Array
(
[id] => 17863587
[patent_doc_number] => 11444752
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-13
[patent_title] => Systems and methods for data encryption and decryption in data transmission
[patent_app_type] => utility
[patent_app_number] => 16/726871
[patent_app_country] => US
[patent_app_date] => 2019-12-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 19949
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16726871
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/726871 | Systems and methods for data encryption and decryption in data transmission | Dec 24, 2019 | Issued |
Array
(
[id] => 16209283
[patent_doc_number] => 20200242273
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-30
[patent_title] => MEMORY CHIP HAVING SECURITY VERIFICATION FUNCTION AND MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/726284
[patent_app_country] => US
[patent_app_date] => 2019-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2989
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16726284
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/726284 | Memory chip having security verification function and memory device | Dec 23, 2019 | Issued |
Array
(
[id] => 16417631
[patent_doc_number] => 10825531
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-11-03
[patent_title] => Semiconductor memory device including page buffers
[patent_app_type] => utility
[patent_app_number] => 16/723899
[patent_app_country] => US
[patent_app_date] => 2019-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 9290
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16723899
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/723899 | Semiconductor memory device including page buffers | Dec 19, 2019 | Issued |
Array
(
[id] => 17402632
[patent_doc_number] => 20220044723
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-10
[patent_title] => SIGNAL DEVELOPMENT CACHING IN A MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/414296
[patent_app_country] => US
[patent_app_date] => 2019-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 49604
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -37
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17414296
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/414296 | Signal development caching in a memory device | Dec 19, 2019 | Issued |
Array
(
[id] => 16495531
[patent_doc_number] => 10861578
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-12-08
[patent_title] => Distributed memory repair network
[patent_app_type] => utility
[patent_app_number] => 16/718535
[patent_app_country] => US
[patent_app_date] => 2019-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5586
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16718535
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/718535 | Distributed memory repair network | Dec 17, 2019 | Issued |
Array
(
[id] => 16880921
[patent_doc_number] => 11031077
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-08
[patent_title] => Resistance variable memory device
[patent_app_type] => utility
[patent_app_number] => 16/715343
[patent_app_country] => US
[patent_app_date] => 2019-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 6075
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715343
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/715343 | Resistance variable memory device | Dec 15, 2019 | Issued |
Array
(
[id] => 16887386
[patent_doc_number] => 20210173583
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-10
[patent_title] => MEMORY DEVICE WITH MICROBUMPS TO TRANSMIT DATA FOR A MACHINE LEARNING OPERATION
[patent_app_type] => utility
[patent_app_number] => 16/703091
[patent_app_country] => US
[patent_app_date] => 2019-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17828
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16703091
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/703091 | Memory device with microbumps to transmit data for a machine learning operation | Dec 3, 2019 | Issued |
Array
(
[id] => 15717175
[patent_doc_number] => 20200105355
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-02
[patent_title] => MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/699981
[patent_app_country] => US
[patent_app_date] => 2019-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14160
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16699981
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/699981 | Memory device | Dec 1, 2019 | Issued |
Array
(
[id] => 16067209
[patent_doc_number] => 10692564
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-23
[patent_title] => Memory cell sensing based on precharging an access line using a sense amplifier
[patent_app_type] => utility
[patent_app_number] => 16/701028
[patent_app_country] => US
[patent_app_date] => 2019-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 25635
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16701028
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/701028 | Memory cell sensing based on precharging an access line using a sense amplifier | Dec 1, 2019 | Issued |