Search

David S. Blum

Examiner (ID: 16757, Phone: (571)272-1687 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
1924
Issued Applications
1781
Pending Applications
10
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16386748 [patent_doc_number] => 10811594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Process for hard mask development for MRAM pillar formation using photolithography [patent_app_type] => utility [patent_app_number] => 15/857351 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3429 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857351 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/857351
Process for hard mask development for MRAM pillar formation using photolithography Dec 27, 2017 Issued
Array ( [id] => 13582241 [patent_doc_number] => 20180342669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => METHOD OF MANUFACTURING A MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR CHIP INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 15/856256 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15856256 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/856256
Method of manufacturing a magnetoresistive random access memory device and method of manufacturing a semiconductor chip including the same Dec 27, 2017 Issued
Array ( [id] => 13283671 [patent_doc_number] => 10153427 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-11 [patent_title] => Magnetic tunnel junction (MTJ) performance by introducing oxidants to methanol with or without noble gas during MTJ etch [patent_app_type] => utility [patent_app_number] => 15/856129 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 6327 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15856129 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/856129
Magnetic tunnel junction (MTJ) performance by introducing oxidants to methanol with or without noble gas during MTJ etch Dec 27, 2017 Issued
Array ( [id] => 14542957 [patent_doc_number] => 20190207100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => PROCESS FOR IMPROVING PHOTORESIST PILLAR ADHESION DURING MRAM FABRICATION [patent_app_type] => utility [patent_app_number] => 15/857318 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2958 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857318 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/857318
Process for improving photoresist pillar adhesion during MRAM fabrication Dec 27, 2017 Issued
Array ( [id] => 14301171 [patent_doc_number] => 10290719 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-14 [patent_title] => Indium gallium arsenide metal oxide semiconductor field effect transistor having a low contact resistance to metal electrode [patent_app_type] => utility [patent_app_number] => 15/855273 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6795 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855273 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/855273
Indium gallium arsenide metal oxide semiconductor field effect transistor having a low contact resistance to metal electrode Dec 26, 2017 Issued
Array ( [id] => 14094213 [patent_doc_number] => 10243021 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-26 [patent_title] => Steep slope field-effect transistor (FET) for a perpendicular magnetic tunnel junction (PMTJ) [patent_app_type] => utility [patent_app_number] => 15/855953 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9983 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855953 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/855953
Steep slope field-effect transistor (FET) for a perpendicular magnetic tunnel junction (PMTJ) Dec 26, 2017 Issued
Array ( [id] => 13785605 [patent_doc_number] => 20190006341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => SEMICONDCUTOR DEVICE PACKAGE AND METHOD OF FORMING SEMICONDCUTOR DEVICE PACKAGE [patent_app_type] => utility [patent_app_number] => 15/854762 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854762 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/854762
Semiconductor device package and method of forming semiconductor device package Dec 26, 2017 Issued
Array ( [id] => 14252879 [patent_doc_number] => 10276648 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-30 [patent_title] => Plasma treatment for thin film resistors on integrated circuits [patent_app_type] => utility [patent_app_number] => 15/855576 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 4082 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855576 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/855576
Plasma treatment for thin film resistors on integrated circuits Dec 26, 2017 Issued
Array ( [id] => 14178097 [patent_doc_number] => 10263071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Method of manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 15/854072 [patent_app_country] => US [patent_app_date] => 2017-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6896 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854072 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/854072
Method of manufacturing semiconductor device Dec 25, 2017 Issued
Array ( [id] => 13306873 [patent_doc_number] => 20180204973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => LIGHT-EMITTING DIODE STRUCTURE, TRANSFER ASSEMBLY, AND TRANSFER METHOD USING THE SAME [patent_app_type] => utility [patent_app_number] => 15/853778 [patent_app_country] => US [patent_app_date] => 2017-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9335 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15853778 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/853778
Light-emitting diode structure, transfer assembly, and transfer method using the same Dec 22, 2017 Issued
Array ( [id] => 13921793 [patent_doc_number] => 10205021 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-12 [patent_title] => Method of fabrication of a semiconductor substrate having at least a tensilely strained semiconductor portion [patent_app_type] => utility [patent_app_number] => 15/852671 [patent_app_country] => US [patent_app_date] => 2017-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 5949 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15852671 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/852671
Method of fabrication of a semiconductor substrate having at least a tensilely strained semiconductor portion Dec 21, 2017 Issued
Array ( [id] => 14178109 [patent_doc_number] => 10263077 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-16 [patent_title] => Method of fabricating a FET transistor having a strained channel [patent_app_type] => utility [patent_app_number] => 15/852681 [patent_app_country] => US [patent_app_date] => 2017-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5796 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15852681 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/852681
Method of fabricating a FET transistor having a strained channel Dec 21, 2017 Issued
Array ( [id] => 14769139 [patent_doc_number] => 10395971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Dam laminate isolation substrate [patent_app_type] => utility [patent_app_number] => 15/852532 [patent_app_country] => US [patent_app_date] => 2017-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2881 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15852532 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/852532
Dam laminate isolation substrate Dec 21, 2017 Issued
Array ( [id] => 13306467 [patent_doc_number] => 20180204770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => REMOVABLE TEMPORARY PROTECTIVE LAYERS FOR USE IN SEMICONDUCTOR MANUFACTURING [patent_app_type] => utility [patent_app_number] => 15/849988 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6214 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15849988 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/849988
Removable temporary protective layers for use in semiconductor manufacturing Dec 20, 2017 Issued
Array ( [id] => 14281041 [patent_doc_number] => 20190137805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => AN ARRAY SUBSTRATE AND A DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 15/743249 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5323 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15743249 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/743249
Array substrate and a display panel Dec 20, 2017 Issued
Array ( [id] => 13320585 [patent_doc_number] => 20180211830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A CLEANING COMPOSITION FOR AN ADHESIVE LAYER [patent_app_type] => utility [patent_app_number] => 15/841946 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5739 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15841946 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/841946
Method of manufacturing a semiconductor device and a cleaning composition for an adhesive layer Dec 13, 2017 Issued
Array ( [id] => 13243327 [patent_doc_number] => 10134875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Method for fabricating a transistor having a vertical channel having nano layers [patent_app_type] => utility [patent_app_number] => 15/842245 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 41 [patent_no_of_words] => 7415 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15842245 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/842245
Method for fabricating a transistor having a vertical channel having nano layers Dec 13, 2017 Issued
Array ( [id] => 14125729 [patent_doc_number] => 10249730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-02 [patent_title] => Controlling gate profile by inter-layer dielectric (ILD) nanolaminates [patent_app_type] => utility [patent_app_number] => 15/838312 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4944 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15838312 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/838312
Controlling gate profile by inter-layer dielectric (ILD) nanolaminates Dec 10, 2017 Issued
Array ( [id] => 12650682 [patent_doc_number] => 20180108725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/834564 [patent_app_country] => US [patent_app_date] => 2017-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9953 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15834564 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/834564
Display device and manufacturing method thereof Dec 6, 2017 Issued
Array ( [id] => 12693181 [patent_doc_number] => 20180122893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => HIGH-K METAL-INSULATOR-METAL CAPACITOR AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/832898 [patent_app_country] => US [patent_app_date] => 2017-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15832898 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/832898
High-K metal-insulator-metal capacitor and method of manufacturing the same Dec 5, 2017 Issued
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