Search

David Silver

Examiner (ID: 13787, Phone: (571)272-8634 , Office: P/2123 )

Most Active Art Unit
2128
Art Unit(s)
2128, 2123, 2127, OPIM, OPA
Total Applications
331
Issued Applications
198
Pending Applications
10
Abandoned Applications
124

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 576880 [patent_doc_number] => 07162411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-09 [patent_title] => 'Dynamic data trace output scheme' [patent_app_type] => utility [patent_app_number] => 10/302026 [patent_app_country] => US [patent_app_date] => 2002-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6722 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/162/07162411.pdf [firstpage_image] =>[orig_patent_app_number] => 10302026 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/302026
Dynamic data trace output scheme Nov 21, 2002 Issued
Array ( [id] => 7472622 [patent_doc_number] => 20040102950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Stalling CPU pipeline to prevent corruption in trace while maintaining coherency with asynchronous events' [patent_app_type] => new [patent_app_number] => 10/302022 [patent_app_country] => US [patent_app_date] => 2002-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4849 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20040102950.pdf [firstpage_image] =>[orig_patent_app_number] => 10302022 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/302022
Stalling CPU pipeline to prevent corruption in trace while maintaining coherency with asynchronous events Nov 21, 2002 Issued
Array ( [id] => 7676523 [patent_doc_number] => 20040153304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Precise detection of triggers and trigger ordering for asynchronous events' [patent_app_type] => new [patent_app_number] => 10/301900 [patent_app_country] => US [patent_app_date] => 2002-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4015 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20040153304.pdf [firstpage_image] =>[orig_patent_app_number] => 10301900 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/301900
Precise detection of triggers and trigger ordering for asynchronous events Nov 21, 2002 Issued
Array ( [id] => 730121 [patent_doc_number] => 07047178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Emulation pause and reset tracing of multiple sync points pointing to different addresses' [patent_app_type] => utility [patent_app_number] => 10/301896 [patent_app_country] => US [patent_app_date] => 2002-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 7527 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/047/07047178.pdf [firstpage_image] =>[orig_patent_app_number] => 10301896 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/301896
Emulation pause and reset tracing of multiple sync points pointing to different addresses Nov 21, 2002 Issued
Array ( [id] => 7472539 [patent_doc_number] => 20040102936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Method and system for designing and evaluating linear polymers' [patent_app_type] => new [patent_app_number] => 10/302596 [patent_app_country] => US [patent_app_date] => 2002-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5006 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20040102936.pdf [firstpage_image] =>[orig_patent_app_number] => 10302596 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/302596
Method and system for designing and evaluating linear polymers Nov 21, 2002 Abandoned
Array ( [id] => 632953 [patent_doc_number] => 07133821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-07 [patent_title] => 'Read FIFO scheduling for multiple streams while maintaining coherency' [patent_app_type] => utility [patent_app_number] => 10/302191 [patent_app_country] => US [patent_app_date] => 2002-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5441 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/133/07133821.pdf [firstpage_image] =>[orig_patent_app_number] => 10302191 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/302191
Read FIFO scheduling for multiple streams while maintaining coherency Nov 21, 2002 Issued
Array ( [id] => 7172060 [patent_doc_number] => 20040078176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques' [patent_app_type] => new [patent_app_number] => 10/274861 [patent_app_country] => US [patent_app_date] => 2002-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4179 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20040078176.pdf [firstpage_image] =>[orig_patent_app_number] => 10274861 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/274861
Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques Oct 20, 2002 Issued
Array ( [id] => 106023 [patent_doc_number] => 07729898 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-01 [patent_title] => 'Methods and apparatus for implementing logic functions on a heterogeneous programmable device' [patent_app_type] => utility [patent_app_number] => 10/274006 [patent_app_country] => US [patent_app_date] => 2002-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5199 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/729/07729898.pdf [firstpage_image] =>[orig_patent_app_number] => 10274006 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/274006
Methods and apparatus for implementing logic functions on a heterogeneous programmable device Oct 16, 2002 Issued
Array ( [id] => 6818767 [patent_doc_number] => 20030069725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'Deterministic method of experimental design' [patent_app_type] => new [patent_app_number] => 10/268272 [patent_app_country] => US [patent_app_date] => 2002-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3570 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20030069725.pdf [firstpage_image] =>[orig_patent_app_number] => 10268272 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/268272
Deterministic method of experimental design Oct 8, 2002 Abandoned
Array ( [id] => 828876 [patent_doc_number] => 07403878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'Using nodes for representing hyper-edges in process models' [patent_app_type] => utility [patent_app_number] => 10/265940 [patent_app_country] => US [patent_app_date] => 2002-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4310 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/403/07403878.pdf [firstpage_image] =>[orig_patent_app_number] => 10265940 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/265940
Using nodes for representing hyper-edges in process models Oct 6, 2002 Issued
Array ( [id] => 7282426 [patent_doc_number] => 20040064803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Validation system and method' [patent_app_type] => new [patent_app_number] => 10/256791 [patent_app_country] => US [patent_app_date] => 2002-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2369 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20040064803.pdf [firstpage_image] =>[orig_patent_app_number] => 10256791 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/256791
Validation system and method Sep 26, 2002 Abandoned
Array ( [id] => 4536326 [patent_doc_number] => 07953588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Method and system for efficient emulation of multiprocessor address translation on a multiprocessor host' [patent_app_type] => utility [patent_app_number] => 10/244559 [patent_app_country] => US [patent_app_date] => 2002-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6720 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/953/07953588.pdf [firstpage_image] =>[orig_patent_app_number] => 10244559 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/244559
Method and system for efficient emulation of multiprocessor address translation on a multiprocessor host Sep 16, 2002 Issued
Array ( [id] => 6721839 [patent_doc_number] => 20030055529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'System for automatically changing computer system configuration' [patent_app_type] => new [patent_app_number] => 10/235710 [patent_app_country] => US [patent_app_date] => 2002-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 17132 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20030055529.pdf [firstpage_image] =>[orig_patent_app_number] => 10235710 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/235710
System for automatically changing computer system configuration Sep 5, 2002 Abandoned
Array ( [id] => 7414067 [patent_doc_number] => 20040025183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Optimization of personal television' [patent_app_type] => new [patent_app_number] => 10/210836 [patent_app_country] => US [patent_app_date] => 2002-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3537 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20040025183.pdf [firstpage_image] =>[orig_patent_app_number] => 10210836 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/210836
Optimization of personal television Jul 30, 2002 Abandoned
Array ( [id] => 7405237 [patent_doc_number] => 20040019474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Method and apparatus to facilitate detecting a slow node in a circuit layout' [patent_app_type] => new [patent_app_number] => 10/207699 [patent_app_country] => US [patent_app_date] => 2002-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2298 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20040019474.pdf [firstpage_image] =>[orig_patent_app_number] => 10207699 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/207699
Method and apparatus to facilitate detecting a slow node in a circuit layout Jul 28, 2002 Abandoned
Array ( [id] => 7458459 [patent_doc_number] => 20040010781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-15 [patent_title] => 'Parameter parsing system' [patent_app_type] => new [patent_app_number] => 10/194474 [patent_app_country] => US [patent_app_date] => 2002-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11251 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20040010781.pdf [firstpage_image] =>[orig_patent_app_number] => 10194474 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/194474
Parameter parsing system Jul 11, 2002 Abandoned
Array ( [id] => 7447222 [patent_doc_number] => 20040003378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Method and system providing access to application running on simulated system' [patent_app_type] => new [patent_app_number] => 10/187647 [patent_app_country] => US [patent_app_date] => 2002-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4090 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20040003378.pdf [firstpage_image] =>[orig_patent_app_number] => 10187647 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/187647
Method and system providing access to application running on simulated system Jun 30, 2002 Abandoned
Array ( [id] => 7441090 [patent_doc_number] => 20040002840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Magnetostatic modeling methods and systems for use with boundary element modeling' [patent_app_type] => new [patent_app_number] => 10/184677 [patent_app_country] => US [patent_app_date] => 2002-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9560 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20040002840.pdf [firstpage_image] =>[orig_patent_app_number] => 10184677 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/184677
Magnetostatic modeling methods and systems for use with boundary element modeling Jun 25, 2002 Issued
Array ( [id] => 6805825 [patent_doc_number] => 20030233219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-18 [patent_title] => 'Method and apparatus emulating read only memories with combinatorial logic networks, and methods and apparatus generating read only memory emulator combinatorial logic networks' [patent_app_type] => new [patent_app_number] => 10/155502 [patent_app_country] => US [patent_app_date] => 2002-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 11127 [patent_no_of_claims] => 126 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20030233219.pdf [firstpage_image] =>[orig_patent_app_number] => 10155502 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/155502
Method and apparatus emulating read only memories with combinatorial logic networks, and methods and apparatus generating read only memory emulator combinatorial logic networks May 22, 2002 Abandoned
Array ( [id] => 6461685 [patent_doc_number] => 20020178433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Method and apparatus to enable flexible and direct navigation within a graphical representation of an organization' [patent_app_type] => new [patent_app_number] => 10/150307 [patent_app_country] => US [patent_app_date] => 2002-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2908 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20020178433.pdf [firstpage_image] =>[orig_patent_app_number] => 10150307 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/150307
Method and apparatus to enable flexible and direct navigation within a graphical representation of an organization May 16, 2002 Abandoned
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