Search

David Silver

Examiner (ID: 8712, Phone: (571)272-8634 , Office: P/2123 )

Most Active Art Unit
2128
Art Unit(s)
OPA, OPIM, 2123, 2128, 2127
Total Applications
331
Issued Applications
198
Pending Applications
10
Abandoned Applications
124

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17108078 [patent_doc_number] => 11128309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Digital calibration method, digital calibration device and true random number generator circuit [patent_app_type] => utility [patent_app_number] => 17/122034 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8995 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122034 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/122034
Digital calibration method, digital calibration device and true random number generator circuit Dec 14, 2020 Issued
Array ( [id] => 16921409 [patent_doc_number] => 20210194501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => METHOD FOR COMPRESSING BEHAVIOR EVENT IN COMPUTER AND COMPUTER DEVICE THEREFOR [patent_app_type] => utility [patent_app_number] => 17/122261 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2659 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122261 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/122261
Method for compressing behavior event in computer and computer device therefor Dec 14, 2020 Issued
Array ( [id] => 16889696 [patent_doc_number] => 20210175893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => ANALOG-TO-DIGITAL CONVERTER USING A PIPELINED MEMRISTIVE NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 17/116144 [patent_app_country] => US [patent_app_date] => 2020-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17116144 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/116144
Analog-to-digital converter using a pipelined memristive neural network Dec 8, 2020 Issued
Array ( [id] => 17661599 [patent_doc_number] => 20220182064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => LOW INTEGRAL NON-LINEARITY DIGITAL-TO-TIME CONVERTER FOR FRACTIONAL-N PLLS [patent_app_type] => utility [patent_app_number] => 17/115570 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115570 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115570
Low integral non-linearity digital-to-time converter for fractional-N PLLS Dec 7, 2020 Issued
Array ( [id] => 17225305 [patent_doc_number] => 11177819 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-16 [patent_title] => Power and area efficient digital-to-time converter with improved stability [patent_app_type] => utility [patent_app_number] => 17/111208 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5611 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111208 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/111208
Power and area efficient digital-to-time converter with improved stability Dec 2, 2020 Issued
Array ( [id] => 17271001 [patent_doc_number] => 11196437 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-12-07 [patent_title] => System and method for testing an analog-to-digital converter [patent_app_type] => utility [patent_app_number] => 17/108624 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 13298 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108624 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/108624
System and method for testing an analog-to-digital converter Nov 30, 2020 Issued
Array ( [id] => 16859161 [patent_doc_number] => 20210159906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => ANALOG TO DIGITAL CONVERTER [patent_app_type] => utility [patent_app_number] => 17/105359 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2170 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17105359 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/105359
ANALOG TO DIGITAL CONVERTER Nov 24, 2020 Abandoned
Array ( [id] => 16859163 [patent_doc_number] => 20210159908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => SYSTEM AND METHOD FOR BACKGROUND CALIBRATION OF TIME INTERLEAVED ADC [patent_app_type] => utility [patent_app_number] => 17/105366 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1541 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17105366 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/105366
System and method for background calibration of time interleaved ADC Nov 24, 2020 Issued
Array ( [id] => 16859162 [patent_doc_number] => 20210159907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => CURRENT STEERING DIGITAL TO ANALOG CONVERTER (DAC) SYSTEM TO PERFORM DAC STATIC LINEARITY CALIBRATION [patent_app_type] => utility [patent_app_number] => 17/105363 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1564 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17105363 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/105363
Current steering digital to analog converter (DAC) system to perform DAC static linearity calibration Nov 24, 2020 Issued
Array ( [id] => 17254691 [patent_doc_number] => 11190199 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-30 [patent_title] => Asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) timing adjustment based on output statistics [patent_app_type] => utility [patent_app_number] => 17/103652 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103652 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103652
Asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) timing adjustment based on output statistics Nov 23, 2020 Issued
Array ( [id] => 16966910 [patent_doc_number] => 20210218409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => ANALOG TO DIGITAL CONVERTER DEVICE AND CAPACITOR WEIGHT CALIBRATION METHOD [patent_app_type] => utility [patent_app_number] => 17/099827 [patent_app_country] => US [patent_app_date] => 2020-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17099827 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/099827
Analog to digital converter device and capacitor weight calibration method Nov 16, 2020 Issued
Array ( [id] => 16859166 [patent_doc_number] => 20210159911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => A/D CONVERTER [patent_app_type] => utility [patent_app_number] => 17/098711 [patent_app_country] => US [patent_app_date] => 2020-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17098711 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/098711
A/D converter Nov 15, 2020 Issued
Array ( [id] => 16678406 [patent_doc_number] => 20210067172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => Guaranteed Data Compression [patent_app_type] => utility [patent_app_number] => 17/097359 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097359 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/097359
Guaranteed data compression Nov 12, 2020 Issued
Array ( [id] => 17153182 [patent_doc_number] => 11146281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Multi-stage switched capacitor circuit and operation method thereof [patent_app_type] => utility [patent_app_number] => 17/096989 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4823 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17096989 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/096989
Multi-stage switched capacitor circuit and operation method thereof Nov 12, 2020 Issued
Array ( [id] => 17600282 [patent_doc_number] => 20220149856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => BRIDGE SENSOR DC ERROR CANCELLATION SCHEME [patent_app_type] => utility [patent_app_number] => 17/095701 [patent_app_country] => US [patent_app_date] => 2020-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4768 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17095701 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/095701
BRIDGE SENSOR DC ERROR CANCELLATION SCHEME Nov 10, 2020 Abandoned
Array ( [id] => 17574852 [patent_doc_number] => 11323131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Delay-based spread spectrum clock generator circuit [patent_app_type] => utility [patent_app_number] => 17/089090 [patent_app_country] => US [patent_app_date] => 2020-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3354 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089090 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/089090
Delay-based spread spectrum clock generator circuit Nov 3, 2020 Issued
Array ( [id] => 16724641 [patent_doc_number] => 20210091788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => ENTROPY AGNOSTIC DATA ENCODING AND DECODING [patent_app_type] => utility [patent_app_number] => 17/089360 [patent_app_country] => US [patent_app_date] => 2020-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089360 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/089360
Entropy agnostic data encoding and decoding Nov 3, 2020 Issued
Array ( [id] => 17240123 [patent_doc_number] => 11184018 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-23 [patent_title] => Mismatch and timing correction technique for mixing-mode digital-to-analog converter (DAC) [patent_app_type] => utility [patent_app_number] => 17/087234 [patent_app_country] => US [patent_app_date] => 2020-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6932 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087234 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/087234
Mismatch and timing correction technique for mixing-mode digital-to-analog converter (DAC) Nov 1, 2020 Issued
Array ( [id] => 16905776 [patent_doc_number] => 20210184692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => DIGITAL TO ANALOG CONVERTERS [patent_app_type] => utility [patent_app_number] => 17/086949 [patent_app_country] => US [patent_app_date] => 2020-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11622 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17086949 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/086949
Digital to analog converters Nov 1, 2020 Issued
Array ( [id] => 17211275 [patent_doc_number] => 11171664 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-09 [patent_title] => Digitally enhanced digital-to-analog converter resolution [patent_app_type] => utility [patent_app_number] => 17/085520 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9214 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085520 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085520
Digitally enhanced digital-to-analog converter resolution Oct 29, 2020 Issued
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