Search

David Ton

Examiner (ID: 5351, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2782, 2784, 2117, 2138, 2133, 2317
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8843381 [patent_doc_number] => 20130139009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-30 [patent_title] => 'SCHEDULING FOR ENHANCING COMMUNICATION PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 13/503827 [patent_app_country] => US [patent_app_date] => 2011-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7761 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13503827 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/503827
Scheduling for enhancing communication performance Nov 27, 2011 Issued
Array ( [id] => 8438253 [patent_doc_number] => 08286038 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-09 [patent_title] => 'Method and apparatus for managing disc defects using updateable DMA, and disc thereof' [patent_app_type] => utility [patent_app_number] => 13/301014 [patent_app_country] => US [patent_app_date] => 2011-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 6638 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13301014 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/301014
Method and apparatus for managing disc defects using updateable DMA, and disc thereof Nov 20, 2011 Issued
Array ( [id] => 8823885 [patent_doc_number] => 20130124930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'CONTROLLING IPSEC OFFLOAD ENABLEMENT DURING HARDWARE FAILURES' [patent_app_type] => utility [patent_app_number] => 13/297620 [patent_app_country] => US [patent_app_date] => 2011-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4170 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13297620 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/297620
Controlling IPSec offload enablement during hardware failures Nov 15, 2011 Issued
Array ( [id] => 8794315 [patent_doc_number] => 20130111284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'ADAPTIVE, WIRELESS AUTOMATIC IDENTIFICATION SYSTEM PILOT PORT INTERFACE' [patent_app_type] => utility [patent_app_number] => 13/287724 [patent_app_country] => US [patent_app_date] => 2011-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3915 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13287724 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/287724
Adaptive, wireless automatic identification system pilot port interface Nov 1, 2011 Issued
Array ( [id] => 8794310 [patent_doc_number] => 20130111279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'SYSTEMS AND METHODS OF GENERATING A REPLACEMENT DEFAULT READ THRESHOLD' [patent_app_type] => utility [patent_app_number] => 13/287299 [patent_app_country] => US [patent_app_date] => 2011-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6523 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13287299 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/287299
Systems and methods of generating a replacement default read threshold Nov 1, 2011 Issued
Array ( [id] => 8472754 [patent_doc_number] => 08301947 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-30 [patent_title] => 'Dynamic scan chain grouping' [patent_app_type] => utility [patent_app_number] => 13/285316 [patent_app_country] => US [patent_app_date] => 2011-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5640 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13285316 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/285316
Dynamic scan chain grouping Oct 30, 2011 Issued
Array ( [id] => 9049320 [patent_doc_number] => 08543878 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-24 [patent_title] => 'Apparatus and a method to test a parametric structure utilizing logical sensing' [patent_app_type] => utility [patent_app_number] => 13/284830 [patent_app_country] => US [patent_app_date] => 2011-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5117 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13284830 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/284830
Apparatus and a method to test a parametric structure utilizing logical sensing Oct 27, 2011 Issued
Array ( [id] => 9077539 [patent_doc_number] => 08555131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Techniques to control power consumption in an iterative decoder by control of node configurations' [patent_app_type] => utility [patent_app_number] => 13/275777 [patent_app_country] => US [patent_app_date] => 2011-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 11122 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13275777 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/275777
Techniques to control power consumption in an iterative decoder by control of node configurations Oct 17, 2011 Issued
Array ( [id] => 8746722 [patent_doc_number] => 20130086439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'Systems and Methods for Parameter Selection Using Reliability Information' [patent_app_type] => utility [patent_app_number] => 13/251342 [patent_app_country] => US [patent_app_date] => 2011-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9597 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13251342 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/251342
Systems and methods for parameter selection using reliability information Oct 2, 2011 Issued
Array ( [id] => 9276060 [patent_doc_number] => 08640007 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-28 [patent_title] => 'Method and apparatus for transmitting diagnostic data for a storage device' [patent_app_type] => utility [patent_app_number] => 13/249193 [patent_app_country] => US [patent_app_date] => 2011-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2473 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13249193 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/249193
Method and apparatus for transmitting diagnostic data for a storage device Sep 28, 2011 Issued
Array ( [id] => 7722081 [patent_doc_number] => 20120011416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'ECC CONTROLLER FOR USE IN FLASH MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/241343 [patent_app_country] => US [patent_app_date] => 2011-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4021 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20120011416.pdf [firstpage_image] =>[orig_patent_app_number] => 13241343 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/241343
ECC controller for use in flash memory device and memory system including the same Sep 22, 2011 Issued
Array ( [id] => 8735276 [patent_doc_number] => 20130080845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'INTERFACE WITH UNIVERSAL SERIAL COMMUNICATION' [patent_app_type] => utility [patent_app_number] => 13/239657 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3138 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13239657 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/239657
Interface with universal serial communication Sep 21, 2011 Issued
Array ( [id] => 8568786 [patent_doc_number] => 20120331357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'METHOD AND SYSTEM OF COMPRESSING RAW FABRICATION DATA FOR FAULT DETERMINATION' [patent_app_type] => utility [patent_app_number] => 13/240305 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4715 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13240305 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/240305
Method and system of compressing raw fabrication data for fault determination Sep 21, 2011 Issued
Array ( [id] => 7717784 [patent_doc_number] => 20120007622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'IP CORE DESIGN SUPPORTING USER-ADDED SCAN REGISTER OPTION' [patent_app_type] => utility [patent_app_number] => 13/238564 [patent_app_country] => US [patent_app_date] => 2011-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3569 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20120007622.pdf [firstpage_image] =>[orig_patent_app_number] => 13238564 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/238564
IC with first and second external register present leads Sep 20, 2011 Issued
Array ( [id] => 8360936 [patent_doc_number] => 20120216091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-23 [patent_title] => 'Method of Analyzing the Safety of a Device Employing On Target Hardware Description Language Based Fault Injection' [patent_app_type] => utility [patent_app_number] => 13/238382 [patent_app_country] => US [patent_app_date] => 2011-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2115 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13238382 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/238382
Method of analyzing the safety of a device employing on target hardware description language based fault injection Sep 20, 2011 Issued
Array ( [id] => 8655496 [patent_doc_number] => 08375265 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-12 [patent_title] => 'Delay fault testing using distributed clock dividers' [patent_app_type] => utility [patent_app_number] => 13/231229 [patent_app_country] => US [patent_app_date] => 2011-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2900 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13231229 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/231229
Delay fault testing using distributed clock dividers Sep 12, 2011 Issued
Array ( [id] => 8935718 [patent_doc_number] => 08495440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Fully programmable parallel PRBS generator' [patent_app_type] => utility [patent_app_number] => 13/221543 [patent_app_country] => US [patent_app_date] => 2011-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 9397 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13221543 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/221543
Fully programmable parallel PRBS generator Aug 29, 2011 Issued
Array ( [id] => 9102764 [patent_doc_number] => 08566658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Low-power and area-efficient scan cell for integrated circuit testing' [patent_app_type] => utility [patent_app_number] => 13/216336 [patent_app_country] => US [patent_app_date] => 2011-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4486 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13216336 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/216336
Low-power and area-efficient scan cell for integrated circuit testing Aug 23, 2011 Issued
Array ( [id] => 8693233 [patent_doc_number] => 08392769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Storage device, circuit board, liquid reservoir and system' [patent_app_type] => utility [patent_app_number] => 13/215130 [patent_app_country] => US [patent_app_date] => 2011-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 9047 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13215130 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/215130
Storage device, circuit board, liquid reservoir and system Aug 21, 2011 Issued
Array ( [id] => 8395669 [patent_doc_number] => 20120233513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'METHOD FOR CREATING TEST CLOCK DOMAIN DURING INTEGRATED CIRCUIT DESIGN, AND ASSOCIATED COMPUTER READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 13/213086 [patent_app_country] => US [patent_app_date] => 2011-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3363 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13213086 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/213086
Method for creating test clock domain during integrated circuit design, and associated computer readable medium Aug 18, 2011 Issued
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