
David Ton
Examiner (ID: 9677)
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2317, 2138, 2782, 2784, 2133, 2117 |
| Total Applications | 1397 |
| Issued Applications | 1294 |
| Pending Applications | 31 |
| Abandoned Applications | 75 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8693233
[patent_doc_number] => 08392769
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-03-05
[patent_title] => 'Storage device, circuit board, liquid reservoir and system'
[patent_app_type] => utility
[patent_app_number] => 13/215130
[patent_app_country] => US
[patent_app_date] => 2011-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 9047
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13215130
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/215130 | Storage device, circuit board, liquid reservoir and system | Aug 21, 2011 | Issued |
Array
(
[id] => 8395669
[patent_doc_number] => 20120233513
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-09-13
[patent_title] => 'METHOD FOR CREATING TEST CLOCK DOMAIN DURING INTEGRATED CIRCUIT DESIGN, AND ASSOCIATED COMPUTER READABLE MEDIUM'
[patent_app_type] => utility
[patent_app_number] => 13/213086
[patent_app_country] => US
[patent_app_date] => 2011-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3363
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13213086
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/213086 | Method for creating test clock domain during integrated circuit design, and associated computer readable medium | Aug 18, 2011 | Issued |
Array
(
[id] => 9947638
[patent_doc_number] => 08996965
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-03-31
[patent_title] => 'Error correcting decoding device and error correcting decoding method'
[patent_app_type] => utility
[patent_app_number] => 13/814219
[patent_app_country] => US
[patent_app_date] => 2011-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 12281
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13814219
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/814219 | Error correcting decoding device and error correcting decoding method | Aug 2, 2011 | Issued |
Array
(
[id] => 7588528
[patent_doc_number] => 20110283039
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-11-17
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/191442
[patent_app_country] => US
[patent_app_date] => 2011-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 8966
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0283/20110283039.pdf
[firstpage_image] =>[orig_patent_app_number] => 13191442
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/191442 | Semiconductor device | Jul 25, 2011 | Issued |
Array
(
[id] => 8389095
[patent_doc_number] => 08266503
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-09-11
[patent_title] => 'Apparatus, system, and method for using multi-level cell storage in a single-level cell mode'
[patent_app_type] => utility
[patent_app_number] => 13/175637
[patent_app_country] => US
[patent_app_date] => 2011-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 8167
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13175637
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/175637 | Apparatus, system, and method for using multi-level cell storage in a single-level cell mode | Jun 30, 2011 | Issued |
Array
(
[id] => 8588751
[patent_doc_number] => 20130007572
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-03
[patent_title] => 'System And Method For Look-Aside Parity Based Raid'
[patent_app_type] => utility
[patent_app_number] => 13/170805
[patent_app_country] => US
[patent_app_date] => 2011-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2762
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13170805
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/170805 | System and method for look-aside parity based raid | Jun 27, 2011 | Issued |
Array
(
[id] => 7707597
[patent_doc_number] => 20120001778
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-01-05
[patent_title] => 'SYSTEM AND METHOD FOR MULTI-DIMENSIONAL ENCODING AND DECODING'
[patent_app_type] => utility
[patent_app_number] => 13/171215
[patent_app_country] => US
[patent_app_date] => 2011-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 17772
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13171215
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/171215 | System and method for multi-dimensional encoding and decoding | Jun 27, 2011 | Issued |
Array
(
[id] => 8873043
[patent_doc_number] => 08468431
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-06-18
[patent_title] => 'System and method for multi-dimensional encoding and decoding'
[patent_app_type] => utility
[patent_app_number] => 13/171211
[patent_app_country] => US
[patent_app_date] => 2011-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 17767
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13171211
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/171211 | System and method for multi-dimensional encoding and decoding | Jun 27, 2011 | Issued |
Array
(
[id] => 9257880
[patent_doc_number] => 08621321
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-12-31
[patent_title] => 'System and method for multi-dimensional encoding and decoding'
[patent_app_type] => utility
[patent_app_number] => 13/171214
[patent_app_country] => US
[patent_app_date] => 2011-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 17976
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13171214
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/171214 | System and method for multi-dimensional encoding and decoding | Jun 27, 2011 | Issued |
Array
(
[id] => 10137555
[patent_doc_number] => 09170875
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-10-27
[patent_title] => 'Method for monitoring a data memory'
[patent_app_type] => utility
[patent_app_number] => 13/809764
[patent_app_country] => US
[patent_app_date] => 2011-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 6806
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13809764
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/809764 | Method for monitoring a data memory | Jun 26, 2011 | Issued |
Array
(
[id] => 9379024
[patent_doc_number] => 08683307
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-03-25
[patent_title] => 'Checksum calculation, prediction and validation'
[patent_app_type] => utility
[patent_app_number] => 13/117294
[patent_app_country] => US
[patent_app_date] => 2011-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 5308
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13117294
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/117294 | Checksum calculation, prediction and validation | May 26, 2011 | Issued |
Array
(
[id] => 8810378
[patent_doc_number] => 08448045
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-05-21
[patent_title] => 'Outer code error correction'
[patent_app_type] => utility
[patent_app_number] => 13/116882
[patent_app_country] => US
[patent_app_date] => 2011-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5042
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13116882
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/116882 | Outer code error correction | May 25, 2011 | Issued |
Array
(
[id] => 8985206
[patent_doc_number] => 08516336
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-08-20
[patent_title] => 'Latch arrangement for an electronic digital system, method, data processing program, and computer program product for implementing a latch arrangement'
[patent_app_type] => utility
[patent_app_number] => 13/116365
[patent_app_country] => US
[patent_app_date] => 2011-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4736
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13116365
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/116365 | Latch arrangement for an electronic digital system, method, data processing program, and computer program product for implementing a latch arrangement | May 25, 2011 | Issued |
Array
(
[id] => 9062915
[patent_doc_number] => 08549369
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-10-01
[patent_title] => 'Semiconductor-based test device that implements random logic functions'
[patent_app_type] => utility
[patent_app_number] => 13/116961
[patent_app_country] => US
[patent_app_date] => 2011-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 8360
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13116961
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/116961 | Semiconductor-based test device that implements random logic functions | May 25, 2011 | Issued |
Array
(
[id] => 9102790
[patent_doc_number] => 08566684
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-10-22
[patent_title] => 'Decoding and optimized implementation of SECDED codes over GF(q)'
[patent_app_type] => utility
[patent_app_number] => 13/116976
[patent_app_country] => US
[patent_app_date] => 2011-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 5153
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13116976
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/116976 | Decoding and optimized implementation of SECDED codes over GF(q) | May 25, 2011 | Issued |
Array
(
[id] => 8924025
[patent_doc_number] => 08489974
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-07-16
[patent_title] => 'System, method and computer program product for resolving a data conflict'
[patent_app_type] => utility
[patent_app_number] => 13/116829
[patent_app_country] => US
[patent_app_date] => 2011-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7658
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13116829
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/116829 | System, method and computer program product for resolving a data conflict | May 25, 2011 | Issued |
Array
(
[id] => 7714334
[patent_doc_number] => 20120005558
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-01-05
[patent_title] => 'SYSTEM AND METHOD FOR DATA RECOVERY IN MULTI-LEVEL CELL MEMORIES'
[patent_app_type] => utility
[patent_app_number] => 13/117008
[patent_app_country] => US
[patent_app_date] => 2011-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 17948
[patent_no_of_claims] => 55
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0005/20120005558.pdf
[firstpage_image] =>[orig_patent_app_number] => 13117008
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/117008 | System and method for data recovery in multi-level cell memories | May 25, 2011 | Issued |
Array
(
[id] => 8412620
[patent_doc_number] => 08276031
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-09-25
[patent_title] => 'Scan architecture for full custom blocks with improved scan latch'
[patent_app_type] => utility
[patent_app_number] => 13/111281
[patent_app_country] => US
[patent_app_date] => 2011-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 13227
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13111281
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/111281 | Scan architecture for full custom blocks with improved scan latch | May 18, 2011 | Issued |
Array
(
[id] => 7718645
[patent_doc_number] => 08095839
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-01-10
[patent_title] => 'Position independent testing of circuits'
[patent_app_type] => utility
[patent_app_number] => 13/100726
[patent_app_country] => US
[patent_app_date] => 2011-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 52
[patent_no_of_words] => 27280
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/095/08095839.pdf
[firstpage_image] =>[orig_patent_app_number] => 13100726
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/100726 | Position independent testing of circuits | May 3, 2011 | Issued |
Array
(
[id] => 7809047
[patent_doc_number] => 20120060001
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-08
[patent_title] => 'MEMORY LIFETIME GAUGING SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT'
[patent_app_type] => utility
[patent_app_number] => 13/042237
[patent_app_country] => US
[patent_app_date] => 2011-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8324
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0060/20120060001.pdf
[firstpage_image] =>[orig_patent_app_number] => 13042237
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/042237 | Reducing writes, and estimating and displaying estimated remaining lifetime of non-volatile memories | Mar 6, 2011 | Issued |