Search

David Ton

Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2782, 2117, 2784, 2317, 2133, 2138
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8355092 [patent_doc_number] => 08250439 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-21 [patent_title] => 'ECC bits used as additional register file storage' [patent_app_type] => utility [patent_app_number] => 12/568557 [patent_app_country] => US [patent_app_date] => 2009-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8451 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12568557 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/568557
ECC bits used as additional register file storage Sep 27, 2009 Issued
Array ( [id] => 6125663 [patent_doc_number] => 20110078544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'Error Detection and Correction for External DRAM' [patent_app_type] => utility [patent_app_number] => 12/568642 [patent_app_country] => US [patent_app_date] => 2009-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11659 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20110078544.pdf [firstpage_image] =>[orig_patent_app_number] => 12568642 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/568642
Error detection and correction for external DRAM Sep 27, 2009 Issued
Array ( [id] => 8308723 [patent_doc_number] => 08230276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-24 [patent_title] => 'Writing to memory using adaptive write techniques' [patent_app_type] => utility [patent_app_number] => 12/568035 [patent_app_country] => US [patent_app_date] => 2009-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7891 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12568035 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/568035
Writing to memory using adaptive write techniques Sep 27, 2009 Issued
Array ( [id] => 8546458 [patent_doc_number] => 08321761 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-11-27 [patent_title] => 'ECC bits used as additional register file storage' [patent_app_type] => utility [patent_app_number] => 12/568552 [patent_app_country] => US [patent_app_date] => 2009-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8451 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12568552 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/568552
ECC bits used as additional register file storage Sep 27, 2009 Issued
Array ( [id] => 4441220 [patent_doc_number] => 07971110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'System and method for testing a serial attached small computer system interface' [patent_app_type] => utility [patent_app_number] => 12/566801 [patent_app_country] => US [patent_app_date] => 2009-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1370 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/971/07971110.pdf [firstpage_image] =>[orig_patent_app_number] => 12566801 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/566801
System and method for testing a serial attached small computer system interface Sep 24, 2009 Issued
Array ( [id] => 7993235 [patent_doc_number] => 08078926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-13 [patent_title] => 'Test pin gating for dynamic optimization' [patent_app_type] => utility [patent_app_number] => 12/558611 [patent_app_country] => US [patent_app_date] => 2009-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1556 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/078/08078926.pdf [firstpage_image] =>[orig_patent_app_number] => 12558611 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/558611
Test pin gating for dynamic optimization Sep 13, 2009 Issued
Array ( [id] => 6204118 [patent_doc_number] => 20110066904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'AVOIDING RACE CONDITIONS AT CLOCK DOMAIN CROSSINGS IN AN EDGE BASED SCAN DESIGN' [patent_app_type] => utility [patent_app_number] => 12/557623 [patent_app_country] => US [patent_app_date] => 2009-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5379 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20110066904.pdf [firstpage_image] =>[orig_patent_app_number] => 12557623 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/557623
Avoiding race conditions at clock domain crossings in an edge based scan design Sep 10, 2009 Issued
Array ( [id] => 7682479 [patent_doc_number] => 20100241932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'ERROR DETECTOR/CORRECTOR, MEMORY CONTROLLER, AND SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/556748 [patent_app_country] => US [patent_app_date] => 2009-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7289 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20100241932.pdf [firstpage_image] =>[orig_patent_app_number] => 12556748 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/556748
ERROR DETECTOR/CORRECTOR, MEMORY CONTROLLER, AND SEMICONDUCTOR MEMORY DEVICE Sep 9, 2009 Abandoned
Array ( [id] => 8558221 [patent_doc_number] => 08332706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'Transport layer control device, method for transmitting packet, and method for receiving packet' [patent_app_type] => utility [patent_app_number] => 12/556331 [patent_app_country] => US [patent_app_date] => 2009-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3868 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12556331 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/556331
Transport layer control device, method for transmitting packet, and method for receiving packet Sep 8, 2009 Issued
Array ( [id] => 8033783 [patent_doc_number] => 08145986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes' [patent_app_type] => utility [patent_app_number] => 12/556379 [patent_app_country] => US [patent_app_date] => 2009-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 9204 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/145/08145986.pdf [firstpage_image] =>[orig_patent_app_number] => 12556379 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/556379
Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes Sep 8, 2009 Issued
Array ( [id] => 6008941 [patent_doc_number] => 20110060973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-10 [patent_title] => 'Systems and Methods for Stepped Data Retry in a Storage System' [patent_app_type] => utility [patent_app_number] => 12/556145 [patent_app_country] => US [patent_app_date] => 2009-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6663 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20110060973.pdf [firstpage_image] =>[orig_patent_app_number] => 12556145 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/556145
Systems and methods for stepped data retry in a storage system Sep 8, 2009 Issued
Array ( [id] => 8878816 [patent_doc_number] => 08473800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Method and apparatus for ACK/NACK reporting' [patent_app_type] => utility [patent_app_number] => 12/556213 [patent_app_country] => US [patent_app_date] => 2009-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6275 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12556213 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/556213
Method and apparatus for ACK/NACK reporting Sep 8, 2009 Issued
Array ( [id] => 6006494 [patent_doc_number] => 20110058631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-10 [patent_title] => 'Systems and Methods for Enhanced Flaw Scan in a Data Processing Device' [patent_app_type] => utility [patent_app_number] => 12/556180 [patent_app_country] => US [patent_app_date] => 2009-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11863 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20110058631.pdf [firstpage_image] =>[orig_patent_app_number] => 12556180 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/556180
Systems and methods for enhanced flaw scan in a data processing device Sep 8, 2009 Issued
Array ( [id] => 4606410 [patent_doc_number] => 07987396 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-26 [patent_title] => 'Reducing bit-error rate using adaptive decision feedback equalization' [patent_app_type] => utility [patent_app_number] => 12/556483 [patent_app_country] => US [patent_app_date] => 2009-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5114 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/987/07987396.pdf [firstpage_image] =>[orig_patent_app_number] => 12556483 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/556483
Reducing bit-error rate using adaptive decision feedback equalization Sep 8, 2009 Issued
Array ( [id] => 6524560 [patent_doc_number] => 20100211837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'Semiconductor test system with self-inspection of memory repair analysis' [patent_app_type] => utility [patent_app_number] => 12/585016 [patent_app_country] => US [patent_app_date] => 2009-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3742 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20100211837.pdf [firstpage_image] =>[orig_patent_app_number] => 12585016 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/585016
Semiconductor test system with self-inspection of memory repair analysis Aug 31, 2009 Issued
Array ( [id] => 6031798 [patent_doc_number] => 20110055648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'SYSTEM AND A METHOD FOR TESTING CONNECTIVITY BETWEEN A FIRST DEVICE AND A SECOND DEVICE' [patent_app_type] => utility [patent_app_number] => 12/550516 [patent_app_country] => US [patent_app_date] => 2009-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4939 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055648.pdf [firstpage_image] =>[orig_patent_app_number] => 12550516 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/550516
System and a method for testing connectivity between a first device and a second device Aug 30, 2009 Issued
Array ( [id] => 9404782 [patent_doc_number] => 08694846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-08 [patent_title] => 'Method for receiving and transmitting data blocks' [patent_app_type] => utility [patent_app_number] => 12/998281 [patent_app_country] => US [patent_app_date] => 2009-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3154 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12998281 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/998281
Method for receiving and transmitting data blocks Aug 26, 2009 Issued
Array ( [id] => 8693241 [patent_doc_number] => 08392777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Centralized MBIST failure information' [patent_app_type] => utility [patent_app_number] => 12/549164 [patent_app_country] => US [patent_app_date] => 2009-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3854 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12549164 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/549164
Centralized MBIST failure information Aug 26, 2009 Issued
Array ( [id] => 7521086 [patent_doc_number] => 07975195 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-05 [patent_title] => 'Scan architecture for full custom blocks with improved scan latch' [patent_app_type] => utility [patent_app_number] => 12/547727 [patent_app_country] => US [patent_app_date] => 2009-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 13280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/975/07975195.pdf [firstpage_image] =>[orig_patent_app_number] => 12547727 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/547727
Scan architecture for full custom blocks with improved scan latch Aug 25, 2009 Issued
Array ( [id] => 4606421 [patent_doc_number] => 07987407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'Handling of hard errors in a cache of a data processing apparatus' [patent_app_type] => utility [patent_app_number] => 12/461695 [patent_app_country] => US [patent_app_date] => 2009-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 18831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 472 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/987/07987407.pdf [firstpage_image] =>[orig_patent_app_number] => 12461695 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/461695
Handling of hard errors in a cache of a data processing apparatus Aug 19, 2009 Issued
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