Search

David Ton

Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2782, 2117, 2784, 2317, 2133, 2138
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10486656 [patent_doc_number] => 20150371676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'RECONSTRUCTIVE ERROR RECOVERY PROCEDURE (ERP) USING RESERVED BUFFER' [patent_app_type] => utility [patent_app_number] => 14/838317 [patent_app_country] => US [patent_app_date] => 2015-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11334 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14838317 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/838317
Reconstructive error recovery procedure (ERP) using reserved buffer Aug 26, 2015 Issued
Array ( [id] => 10597972 [patent_doc_number] => 09319071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Parallel bit interleaver' [patent_app_type] => utility [patent_app_number] => 14/752062 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 56 [patent_no_of_words] => 17665 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752062 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752062
Parallel bit interleaver Jun 25, 2015 Issued
Array ( [id] => 11489277 [patent_doc_number] => 09595349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-14 [patent_title] => 'Hardware apparatuses and methods to check data storage devices for transient faults' [patent_app_type] => utility [patent_app_number] => 14/751113 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 18823 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14751113 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/751113
Hardware apparatuses and methods to check data storage devices for transient faults Jun 24, 2015 Issued
Array ( [id] => 11412406 [patent_doc_number] => 09559726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Use of error correcting code to carry additional data bits' [patent_app_type] => utility [patent_app_number] => 14/740100 [patent_app_country] => US [patent_app_date] => 2015-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 18811 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14740100 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/740100
Use of error correcting code to carry additional data bits Jun 14, 2015 Issued
Array ( [id] => 11244717 [patent_doc_number] => 09470756 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-10-18 [patent_title] => 'Method for using sequential decompression logic for VLSI test in a physically efficient construction' [patent_app_type] => utility [patent_app_number] => 14/738765 [patent_app_country] => US [patent_app_date] => 2015-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12392 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14738765 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/738765
Method for using sequential decompression logic for VLSI test in a physically efficient construction Jun 11, 2015 Issued
Array ( [id] => 11244715 [patent_doc_number] => 09470754 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-10-18 [patent_title] => 'Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serialization' [patent_app_type] => utility [patent_app_number] => 14/737331 [patent_app_country] => US [patent_app_date] => 2015-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 7647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14737331 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/737331
Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serialization Jun 10, 2015 Issued
Array ( [id] => 11340117 [patent_doc_number] => 20160365873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-15 [patent_title] => 'Non-Binary LDPC Codes Over Non-Associative Finite Division Near Rings' [patent_app_type] => utility [patent_app_number] => 14/734749 [patent_app_country] => US [patent_app_date] => 2015-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14734749 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/734749
Non-Binary LDPC Codes Over Non-Associative Finite Division Near Rings Jun 8, 2015 Abandoned
Array ( [id] => 11339400 [patent_doc_number] => 20160365156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-15 [patent_title] => 'BUILT-IN SELF-TEST (BIST) CIRCUIT AND ASSOCIATED BIST METHOD FOR EMBEDDED MEMORIES' [patent_app_type] => utility [patent_app_number] => 14/734041 [patent_app_country] => US [patent_app_date] => 2015-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13112 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14734041 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/734041
Built-in self-test (BIST) circuit and associated BIST method for embedded memories Jun 8, 2015 Issued
Array ( [id] => 11327016 [patent_doc_number] => 20160357628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-08 [patent_title] => 'SELECTIVE ERROR CODING' [patent_app_type] => utility [patent_app_number] => 14/732945 [patent_app_country] => US [patent_app_date] => 2015-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3277 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14732945 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/732945
Selective error coding Jun 7, 2015 Issued
Array ( [id] => 11564794 [patent_doc_number] => 09627388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-18 [patent_title] => 'Memory system having overwrite operation control method thereof' [patent_app_type] => utility [patent_app_number] => 14/731003 [patent_app_country] => US [patent_app_date] => 2015-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 9474 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14731003 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/731003
Memory system having overwrite operation control method thereof Jun 3, 2015 Issued
Array ( [id] => 11579527 [patent_doc_number] => 09634800 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-25 [patent_title] => 'Sub-rate codes within the 10GBASE-T frame structure' [patent_app_type] => utility [patent_app_number] => 14/730083 [patent_app_country] => US [patent_app_date] => 2015-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 30 [patent_no_of_words] => 6474 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14730083 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/730083
Sub-rate codes within the 10GBASE-T frame structure Jun 2, 2015 Issued
Array ( [id] => 10462210 [patent_doc_number] => 20150347225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'SYSTEMS AND METHODS FOR IMPROVING EFFICIENCIES OF A MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/724558 [patent_app_country] => US [patent_app_date] => 2015-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11885 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14724558 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/724558
Systems and methods for improving efficiencies of a memory system May 27, 2015 Issued
Array ( [id] => 10166012 [patent_doc_number] => 09197247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-24 [patent_title] => 'Memory system and error correction method' [patent_app_type] => utility [patent_app_number] => 14/718476 [patent_app_country] => US [patent_app_date] => 2015-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12323 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14718476 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/718476
Memory system and error correction method May 20, 2015 Issued
Array ( [id] => 10577672 [patent_doc_number] => 09300328 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-29 [patent_title] => 'Methodology for improved bit-flipping decoder in 1-read and 2-read scenarios' [patent_app_type] => utility [patent_app_number] => 14/681801 [patent_app_country] => US [patent_app_date] => 2015-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 12133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14681801 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/681801
Methodology for improved bit-flipping decoder in 1-read and 2-read scenarios Apr 7, 2015 Issued
Array ( [id] => 11790705 [patent_doc_number] => 09400311 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-07-26 [patent_title] => 'Method and system of collective failure diagnosis for multiple electronic circuits' [patent_app_type] => utility [patent_app_number] => 14/675365 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11048 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14675365 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/675365
Method and system of collective failure diagnosis for multiple electronic circuits Mar 30, 2015 Issued
Array ( [id] => 10665117 [patent_doc_number] => 20160011260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'On-Chip Service Processor' [patent_app_type] => utility [patent_app_number] => 14/671454 [patent_app_country] => US [patent_app_date] => 2015-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9330 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14671454 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/671454
On-Chip Service Processor Mar 26, 2015 Abandoned
Array ( [id] => 10391867 [patent_doc_number] => 20150276874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'METHOD AND APPARATUS FOR IMPROVING EFFICIENCY OF TESTING INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 14/670033 [patent_app_country] => US [patent_app_date] => 2015-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7369 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14670033 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/670033
Method and apparatus for improving efficiency of testing integrated circuits Mar 25, 2015 Issued
Array ( [id] => 11418087 [patent_doc_number] => 09564922 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-07 [patent_title] => 'Error correction code decoder with stochastic floor mitigation' [patent_app_type] => utility [patent_app_number] => 14/642072 [patent_app_country] => US [patent_app_date] => 2015-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5717 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14642072 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/642072
Error correction code decoder with stochastic floor mitigation Mar 8, 2015 Issued
Array ( [id] => 11238434 [patent_doc_number] => 09465071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-11 [patent_title] => 'Method and apparatus for generating featured scan pattern' [patent_app_type] => utility [patent_app_number] => 14/637311 [patent_app_country] => US [patent_app_date] => 2015-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4495 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14637311 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/637311
Method and apparatus for generating featured scan pattern Mar 2, 2015 Issued
Array ( [id] => 10284406 [patent_doc_number] => 20150169404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'APPARATUS AND METHODS OF PROGRAMMING MEMORY CELLS USING ADJUSTABLE CHARGE STATE LEVEL(S)' [patent_app_type] => utility [patent_app_number] => 14/632343 [patent_app_country] => US [patent_app_date] => 2015-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6041 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14632343 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/632343
Apparatus and methods of programming memory cells using adjustable charge state level(s) Feb 25, 2015 Issued
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