Search

David Ton

Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2782, 2117, 2784, 2317, 2133, 2138
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8194835 [patent_doc_number] => 08185795 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-05-22 [patent_title] => 'Side channel for forward error correction used with long-haul IP links' [patent_app_type] => utility [patent_app_number] => 12/215430 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6055 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/185/08185795.pdf [firstpage_image] =>[orig_patent_app_number] => 12215430 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/215430
Side channel for forward error correction used with long-haul IP links Jun 26, 2008 Issued
Array ( [id] => 7589624 [patent_doc_number] => 07665011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'Method and circuit for reducing SATA transmission data errors by adjusting the period of sending align primitives' [patent_app_type] => utility [patent_app_number] => 12/144309 [patent_app_country] => US [patent_app_date] => 2008-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2496 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/665/07665011.pdf [firstpage_image] =>[orig_patent_app_number] => 12144309 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/144309
Method and circuit for reducing SATA transmission data errors by adjusting the period of sending align primitives Jun 22, 2008 Issued
Array ( [id] => 5396444 [patent_doc_number] => 20090316507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'Generation Of Test Sequences During Memory Built-In Self Testing Of Multiple Memories' [patent_app_type] => utility [patent_app_number] => 12/142912 [patent_app_country] => US [patent_app_date] => 2008-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5531 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0316/20090316507.pdf [firstpage_image] =>[orig_patent_app_number] => 12142912 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/142912
Generation of test sequences during memory built-in self testing of multiple memories Jun 19, 2008 Issued
Array ( [id] => 7726376 [patent_doc_number] => 08099656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-17 [patent_title] => 'Reed solomon decoder' [patent_app_type] => utility [patent_app_number] => 12/214730 [patent_app_country] => US [patent_app_date] => 2008-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/099/08099656.pdf [firstpage_image] =>[orig_patent_app_number] => 12214730 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/214730
Reed solomon decoder Jun 19, 2008 Issued
Array ( [id] => 4665498 [patent_doc_number] => 20080256405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND FOUNDRY TEST ENVIRONMENTS' [patent_app_type] => utility [patent_app_number] => 12/143007 [patent_app_country] => US [patent_app_date] => 2008-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3143 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20080256405.pdf [firstpage_image] =>[orig_patent_app_number] => 12143007 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/143007
COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND FOUNDRY TEST ENVIRONMENTS Jun 19, 2008 Abandoned
Array ( [id] => 5273680 [patent_doc_number] => 20090077456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'Methods and apparatus to generate multiple CRCs' [patent_app_type] => utility [patent_app_number] => 12/213579 [patent_app_country] => US [patent_app_date] => 2008-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5818 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20090077456.pdf [firstpage_image] =>[orig_patent_app_number] => 12213579 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/213579
Methods and apparatus to generate multiple CRCs Jun 19, 2008 Issued
Array ( [id] => 248885 [patent_doc_number] => 07587646 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-08 [patent_title] => 'Test pattern generation in residue networks' [patent_app_type] => utility [patent_app_number] => 12/143043 [patent_app_country] => US [patent_app_date] => 2008-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 9508 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/587/07587646.pdf [firstpage_image] =>[orig_patent_app_number] => 12143043 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/143043
Test pattern generation in residue networks Jun 19, 2008 Issued
Array ( [id] => 28421 [patent_doc_number] => 07797595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Serially decoded digital device testing' [patent_app_type] => utility [patent_app_number] => 12/141284 [patent_app_country] => US [patent_app_date] => 2008-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5733 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/797/07797595.pdf [firstpage_image] =>[orig_patent_app_number] => 12141284 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/141284
Serially decoded digital device testing Jun 17, 2008 Issued
Array ( [id] => 4684055 [patent_doc_number] => 20080250281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'METHODS AND APPARATUS FOR MONITORING INTERNAL SIGNALS IN AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/140266 [patent_app_country] => US [patent_app_date] => 2008-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4898 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20080250281.pdf [firstpage_image] =>[orig_patent_app_number] => 12140266 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/140266
Methods and apparatus for monitoring internal signals in an integrated circuit Jun 16, 2008 Issued
Array ( [id] => 28426 [patent_doc_number] => 07797600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Method and apparatus for testing a ring of non-scan latches with logic built-in self-test' [patent_app_type] => utility [patent_app_number] => 12/139114 [patent_app_country] => US [patent_app_date] => 2008-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5366 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/797/07797600.pdf [firstpage_image] =>[orig_patent_app_number] => 12139114 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/139114
Method and apparatus for testing a ring of non-scan latches with logic built-in self-test Jun 12, 2008 Issued
Array ( [id] => 5375951 [patent_doc_number] => 20090313512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-17 [patent_title] => 'APPARATUS AND METHOD FOR MEMORY CARD TESTING' [patent_app_type] => utility [patent_app_number] => 12/138485 [patent_app_country] => US [patent_app_date] => 2008-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2603 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20090313512.pdf [firstpage_image] =>[orig_patent_app_number] => 12138485 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/138485
Apparatus and method for memory card testing Jun 12, 2008 Issued
Array ( [id] => 146890 [patent_doc_number] => 07694198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-06 [patent_title] => 'Self-repairing of microprocessor array structures' [patent_app_type] => utility [patent_app_number] => 12/138129 [patent_app_country] => US [patent_app_date] => 2008-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4966 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/694/07694198.pdf [firstpage_image] =>[orig_patent_app_number] => 12138129 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/138129
Self-repairing of microprocessor array structures Jun 11, 2008 Issued
Array ( [id] => 7537697 [patent_doc_number] => 08051340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'System and method for balancing delay of signal communication paths through well voltage adjustment' [patent_app_type] => utility [patent_app_number] => 12/136359 [patent_app_country] => US [patent_app_date] => 2008-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3694 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/051/08051340.pdf [firstpage_image] =>[orig_patent_app_number] => 12136359 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/136359
System and method for balancing delay of signal communication paths through well voltage adjustment Jun 9, 2008 Issued
Array ( [id] => 213393 [patent_doc_number] => 07624312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-24 [patent_title] => 'System, apparatus, computer program product for performing operational validation with limited CPU use of a communications network' [patent_app_type] => utility [patent_app_number] => 12/131068 [patent_app_country] => US [patent_app_date] => 2008-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2345 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/624/07624312.pdf [firstpage_image] =>[orig_patent_app_number] => 12131068 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/131068
System, apparatus, computer program product for performing operational validation with limited CPU use of a communications network May 30, 2008 Issued
Array ( [id] => 4586980 [patent_doc_number] => 07849375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Semiconductor test system' [patent_app_type] => utility [patent_app_number] => 12/128057 [patent_app_country] => US [patent_app_date] => 2008-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2452 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/849/07849375.pdf [firstpage_image] =>[orig_patent_app_number] => 12128057 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/128057
Semiconductor test system May 27, 2008 Issued
Array ( [id] => 4947418 [patent_doc_number] => 20080303544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'DELAY MEASURING DEVICE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/127369 [patent_app_country] => US [patent_app_date] => 2008-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7354 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0303/20080303544.pdf [firstpage_image] =>[orig_patent_app_number] => 12127369 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/127369
Delay measuring device and semiconductor device May 26, 2008 Issued
Array ( [id] => 58730 [patent_doc_number] => 07770078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'Integrated circuit communication self-testing' [patent_app_type] => utility [patent_app_number] => 12/153795 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2489 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/770/07770078.pdf [firstpage_image] =>[orig_patent_app_number] => 12153795 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/153795
Integrated circuit communication self-testing May 22, 2008 Issued
Array ( [id] => 4522840 [patent_doc_number] => 07917820 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-29 [patent_title] => 'Testing an embedded core' [patent_app_type] => utility [patent_app_number] => 12/123867 [patent_app_country] => US [patent_app_date] => 2008-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8111 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/917/07917820.pdf [firstpage_image] =>[orig_patent_app_number] => 12123867 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/123867
Testing an embedded core May 19, 2008 Issued
Array ( [id] => 5553985 [patent_doc_number] => 20090287971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'METHOD AND APPARATUS FOR TESTING A RANDOM ACCESS MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/121512 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1197 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20090287971.pdf [firstpage_image] =>[orig_patent_app_number] => 12121512 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/121512
Method and apparatus for testing a random access memory device May 14, 2008 Issued
Array ( [id] => 9284 [patent_doc_number] => 07814386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-12 [patent_title] => 'Built in self test for input/output characterization' [patent_app_type] => utility [patent_app_number] => 12/117268 [patent_app_country] => US [patent_app_date] => 2008-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8079 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/814/07814386.pdf [firstpage_image] =>[orig_patent_app_number] => 12117268 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/117268
Built in self test for input/output characterization May 7, 2008 Issued
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