Search

David Ton

Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2782, 2117, 2784, 2317, 2133, 2138
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4847659 [patent_doc_number] => 20080184067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'Raid system and data recovery apparatus using galois field' [patent_app_type] => utility [patent_app_number] => 12/006994 [patent_app_country] => US [patent_app_date] => 2008-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5667 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20080184067.pdf [firstpage_image] =>[orig_patent_app_number] => 12006994 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/006994
Raid system and data recovery apparatus using galois field Jan 7, 2008 Issued
Array ( [id] => 4754757 [patent_doc_number] => 20080162833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Memory device employing dual clocking for generating systematic code and method thereof' [patent_app_type] => utility [patent_app_number] => 12/000837 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5097 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20080162833.pdf [firstpage_image] =>[orig_patent_app_number] => 12000837 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/000837
Memory device employing dual clocking for generating systematic code and method thereof Dec 17, 2007 Issued
Array ( [id] => 4832590 [patent_doc_number] => 20080131136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'METHOD AND APPARATUS FOR CONVERTING INTERFACE BETWEEN HIGH SPEED DATA HAVING VARIOUS CAPACITIES' [patent_app_type] => utility [patent_app_number] => 11/947349 [patent_app_country] => US [patent_app_date] => 2007-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5423 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20080131136.pdf [firstpage_image] =>[orig_patent_app_number] => 11947349 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/947349
Method and apparatus for converting interface between high speed data having various capacities Nov 28, 2007 Issued
Array ( [id] => 193007 [patent_doc_number] => 07644334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'Requirements-based test generation' [patent_app_type] => utility [patent_app_number] => 11/945021 [patent_app_country] => US [patent_app_date] => 2007-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/644/07644334.pdf [firstpage_image] =>[orig_patent_app_number] => 11945021 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/945021
Requirements-based test generation Nov 25, 2007 Issued
Array ( [id] => 4923806 [patent_doc_number] => 20080072123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'ITERATIVE DECODER EMPLOYING MULTIPLE EXTERNAL CODE ERROR CHECKS TO LOWER THE ERROR FLOOR' [patent_app_type] => utility [patent_app_number] => 11/944320 [patent_app_country] => US [patent_app_date] => 2007-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072123.pdf [firstpage_image] =>[orig_patent_app_number] => 11944320 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/944320
Iterative decoder employing multiple external code error checks to lower the error floor Nov 20, 2007 Issued
Array ( [id] => 146887 [patent_doc_number] => 07694196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-06 [patent_title] => 'Self-diagnostic scheme for detecting errors' [patent_app_type] => utility [patent_app_number] => 11/943428 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3379 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/694/07694196.pdf [firstpage_image] =>[orig_patent_app_number] => 11943428 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/943428
Self-diagnostic scheme for detecting errors Nov 19, 2007 Issued
Array ( [id] => 5277053 [patent_doc_number] => 20090129185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'SEMICONDUCTOR CIRCUITS CAPABLE OF SELF DETECTING DEFECTS' [patent_app_type] => utility [patent_app_number] => 11/941996 [patent_app_country] => US [patent_app_date] => 2007-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20090129185.pdf [firstpage_image] =>[orig_patent_app_number] => 11941996 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/941996
SEMICONDUCTOR CIRCUITS CAPABLE OF SELF DETECTING DEFECTS Nov 18, 2007 Abandoned
Array ( [id] => 8460931 [patent_doc_number] => 08296615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'System and method for generating data migration plan' [patent_app_type] => utility [patent_app_number] => 11/941963 [patent_app_country] => US [patent_app_date] => 2007-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5320 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11941963 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/941963
System and method for generating data migration plan Nov 17, 2007 Issued
Array ( [id] => 4847677 [patent_doc_number] => 20080184085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'SEMICONDUCTOR IC INCLUDING PAD FOR WAFER TEST AND METHOD OF TESTING WAFER INCLUDING SEMICONDUCTOR IC' [patent_app_type] => utility [patent_app_number] => 11/938480 [patent_app_country] => US [patent_app_date] => 2007-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3238 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20080184085.pdf [firstpage_image] =>[orig_patent_app_number] => 11938480 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/938480
Semiconductor IC including pad for wafer test and method of testing wafer including semiconductor IC Nov 11, 2007 Issued
Array ( [id] => 4470170 [patent_doc_number] => 07882404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Backplane emulation technique for automated testing' [patent_app_type] => utility [patent_app_number] => 11/935759 [patent_app_country] => US [patent_app_date] => 2007-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3250 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/882/07882404.pdf [firstpage_image] =>[orig_patent_app_number] => 11935759 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/935759
Backplane emulation technique for automated testing Nov 5, 2007 Issued
Array ( [id] => 5430325 [patent_doc_number] => 20090089635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'Electronic Device Testing System and Method' [patent_app_type] => utility [patent_app_number] => 11/935326 [patent_app_country] => US [patent_app_date] => 2007-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2933 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20090089635.pdf [firstpage_image] =>[orig_patent_app_number] => 11935326 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/935326
Electronic device testing system and method Nov 4, 2007 Issued
Array ( [id] => 4559594 [patent_doc_number] => 07877649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Method and apparatus for testing a memory chip using a common node for multiple inputs and outputs' [patent_app_type] => utility [patent_app_number] => 11/934644 [patent_app_country] => US [patent_app_date] => 2007-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7841 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/877/07877649.pdf [firstpage_image] =>[orig_patent_app_number] => 11934644 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/934644
Method and apparatus for testing a memory chip using a common node for multiple inputs and outputs Nov 1, 2007 Issued
Array ( [id] => 86756 [patent_doc_number] => 07747914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-29 [patent_title] => 'Memory diagnosis test circuit and test method using the same' [patent_app_type] => utility [patent_app_number] => 11/980442 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3256 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/747/07747914.pdf [firstpage_image] =>[orig_patent_app_number] => 11980442 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/980442
Memory diagnosis test circuit and test method using the same Oct 30, 2007 Issued
Array ( [id] => 163398 [patent_doc_number] => 07676707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Device and method for testing SAS channels' [patent_app_type] => utility [patent_app_number] => 11/928591 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2565 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/676/07676707.pdf [firstpage_image] =>[orig_patent_app_number] => 11928591 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/928591
Device and method for testing SAS channels Oct 29, 2007 Issued
Array ( [id] => 5329660 [patent_doc_number] => 20090110137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'FEEDBACK SHIFT REGISTER CONTROL' [patent_app_type] => utility [patent_app_number] => 11/928030 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3723 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20090110137.pdf [firstpage_image] =>[orig_patent_app_number] => 11928030 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/928030
Feedback shift register control Oct 29, 2007 Issued
Array ( [id] => 4592865 [patent_doc_number] => 07853841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Memory cell programming' [patent_app_type] => utility [patent_app_number] => 11/926713 [patent_app_country] => US [patent_app_date] => 2007-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 10202 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/853/07853841.pdf [firstpage_image] =>[orig_patent_app_number] => 11926713 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/926713
Memory cell programming Oct 28, 2007 Issued
Array ( [id] => 4530752 [patent_doc_number] => 07913126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-22 [patent_title] => 'Semiconductor memory device and method of testing same' [patent_app_type] => utility [patent_app_number] => 11/976652 [patent_app_country] => US [patent_app_date] => 2007-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7114 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/913/07913126.pdf [firstpage_image] =>[orig_patent_app_number] => 11976652 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/976652
Semiconductor memory device and method of testing same Oct 25, 2007 Issued
Array ( [id] => 7521103 [patent_doc_number] => 07975212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'Sequential decoding method and apparatus thereof' [patent_app_type] => utility [patent_app_number] => 11/924584 [patent_app_country] => US [patent_app_date] => 2007-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8826 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/975/07975212.pdf [firstpage_image] =>[orig_patent_app_number] => 11924584 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/924584
Sequential decoding method and apparatus thereof Oct 24, 2007 Issued
Array ( [id] => 6620612 [patent_doc_number] => 20100064191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'DIAGNOSTIC DEVICE, DIAGNOSTIC METHOD, PROGRAM, AND RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/513401 [patent_app_country] => US [patent_app_date] => 2007-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6846 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20100064191.pdf [firstpage_image] =>[orig_patent_app_number] => 12513401 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/513401
Diagnostic device, diagnostic method, program, and recording medium Oct 23, 2007 Issued
Array ( [id] => 4940450 [patent_doc_number] => 20080077769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'APPARATUS FOR EFFICIENT LFSR IN A SIMD PROCESSOR' [patent_app_type] => utility [patent_app_number] => 11/923576 [patent_app_country] => US [patent_app_date] => 2007-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5111 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20080077769.pdf [firstpage_image] =>[orig_patent_app_number] => 11923576 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/923576
APPARATUS FOR EFFICIENT LFSR IN A SIMD PROCESSOR Oct 23, 2007 Abandoned
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