
David Ton
Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2782, 2117, 2784, 2317, 2133, 2138 |
| Total Applications | 1397 |
| Issued Applications | 1295 |
| Pending Applications | 31 |
| Abandoned Applications | 75 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 231602
[patent_doc_number] => 07603600
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-10-13
[patent_title] => 'Timing failure remedying apparatus for an integrated circuit, timing failure diagnosing apparatus for an integrated circuit, timing failure diagnosing method for an integrated circuit, integrated circuit, computer readable recording medium recorded thereon a timing failure diagnosing program for an integrated circuit, and computer readable recording medium recorded thereon a timing failure remedying program for an integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/843032
[patent_app_country] => US
[patent_app_date] => 2007-08-22
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 14527
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/603/07603600.pdf
[firstpage_image] =>[orig_patent_app_number] => 11843032
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/843032 | Timing failure remedying apparatus for an integrated circuit, timing failure diagnosing apparatus for an integrated circuit, timing failure diagnosing method for an integrated circuit, integrated circuit, computer readable recording medium recorded thereon a timing failure diagnosing program for an integrated circuit, and computer readable recording medium recorded thereon a timing failure remedying program for an integrated circuit | Aug 21, 2007 | Issued |
Array
(
[id] => 5339234
[patent_doc_number] => 20090055698
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-26
[patent_title] => 'SYSTEM, APPARATUS, AND METHOD FOR MEMORY BUILT-IN SELF TESTING USING MICROCODE SEQUENCERS'
[patent_app_type] => utility
[patent_app_number] => 11/842817
[patent_app_country] => US
[patent_app_date] => 2007-08-21
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[pdf_file] => publications/A1/0055/20090055698.pdf
[firstpage_image] =>[orig_patent_app_number] => 11842817
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/842817 | System, apparatus, and method for memory built-in self testing using microcode sequencers | Aug 20, 2007 | Issued |
Array
(
[id] => 5448113
[patent_doc_number] => 20090049339
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-19
[patent_title] => 'Programmable Diagnostic Memory Module'
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[firstpage_image] =>[orig_patent_app_number] => 11840481
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/840481 | Programmable diagnostic memory module | Aug 16, 2007 | Issued |
Array
(
[id] => 4606420
[patent_doc_number] => 07987406
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-26
[patent_title] => 'Wireless communications apparatus and method'
[patent_app_type] => utility
[patent_app_number] => 12/438319
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/438319 | Wireless communications apparatus and method | Aug 16, 2007 | Issued |
Array
(
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[patent_title] => 'Methodology and system to set JTAG interface'
[patent_app_type] => utility
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[pdf_file] => patents/07/712/07712003.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/838972 | Methodology and system to set JTAG interface | Aug 14, 2007 | Issued |
Array
(
[id] => 5414010
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[patent_title] => 'Systems and Methods for Scan Chain Testing Using Analog Signals'
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Array
(
[id] => 6365121
[patent_doc_number] => 20100251046
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[patent_title] => 'FAILURE PREDICTION CIRCUIT AND METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 12/438576
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[firstpage_image] =>[orig_patent_app_number] => 12438576
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/438576 | Failure prediction circuit and method, and semiconductor integrated circuit | Aug 8, 2007 | Issued |
Array
(
[id] => 7780091
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[patent_title] => 'Rate-adaptive forward error correction for optical transport systems'
[patent_app_type] => utility
[patent_app_number] => 11/834169
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[patent_app_date] => 2007-08-06
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Array
(
[id] => 4735588
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[patent_title] => 'MEMORY DEVICE TESTABLE WITHOUT USING DATA AND DATALESS TEST METHOD'
[patent_app_type] => utility
[patent_app_number] => 11/834502
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[patent_app_date] => 2007-08-06
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Array
(
[id] => 5362994
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[patent_title] => 'Shrink Test Mode to Identify Nth Order Speed Paths'
[patent_app_type] => utility
[patent_app_number] => 11/830116
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Array
(
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[patent_title] => 'Method for Discovering and Isolating Failure of High Speed Traces in a Manufacturing Environment'
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Array
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[id] => 5292171
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/779499 | Apparatus and method for decoding bursts of coded information | Jul 17, 2007 | Issued |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/768336 | Method and system for reliable data transfer | Jun 25, 2007 | Issued |
Array
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