David Ton

Array ( [id] => 5061864 [patent_doc_number] => 20070223503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'DATA TRANSMISSION APPARATUS AND METHOD' [patent_app_type] => utility [patent_app_number] => 11/755635 [patent_app_country] => US [patent_app_date] => 2007-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8465 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20070223503.pdf [firstpage_image] =>[orig_patent_app_number] => 11755635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4976081 [patent_doc_number] => 20070217312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'BINARY DATA ENCODING/DECODING FOR PARALLEL BUS' [patent_app_type] => utility [patent_app_number] => 11/752088 [patent_app_country] => US [patent_app_date] => 2007-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7455 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20070217312.pdf [firstpage_image] =>[orig_patent_app_number] => 11752088 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5292175 [patent_doc_number] => 20090024905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-22 [patent_title] => 'COMBINED DISTORTION ESTIMATION AND ERROR CORRECTION CODING FOR MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 11/996054 [patent_app_country] => US [patent_app_date] => 2007-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 12978 [patent_no_of_claims] => 88 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20090024905.pdf [firstpage_image] =>[orig_patent_app_number] => 11996054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4754947 [patent_doc_number] => 20080163023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'ECC controller for use in flash memory device and memory system including the same' [patent_app_type] => utility [patent_app_number] => 11/785719 [patent_app_country] => US [patent_app_date] => 2007-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3990 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20080163023.pdf [firstpage_image] =>[orig_patent_app_number] => 11785719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8460937 [patent_doc_number] => 08296621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Integrated circuit comprising error correction logic, and a method of error correction' [patent_app_type] => utility [patent_app_number] => 12/593514 [patent_app_country] => US [patent_app_date] => 2007-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5150 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12593514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7813474 [patent_doc_number] => 08136012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-13 [patent_title] => 'Method and system for updating topology changes of a computer network' [patent_app_type] => utility [patent_app_number] => 12/295060 [patent_app_country] => US [patent_app_date] => 2007-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1707 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/136/08136012.pdf [firstpage_image] =>[orig_patent_app_number] => 12295060 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 97438 [patent_doc_number] => 07739564 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-15 [patent_title] => 'Testing an integrated circuit using dedicated function pins' [patent_app_type] => utility [patent_app_number] => 11/726073 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4043 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/739/07739564.pdf [firstpage_image] =>[orig_patent_app_number] => 11726073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4447591 [patent_doc_number] => 07930603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Feature-oriented test program development and execution' [patent_app_type] => utility [patent_app_number] => 11/724448 [patent_app_country] => US [patent_app_date] => 2007-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7602 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/930/07930603.pdf [firstpage_image] =>[orig_patent_app_number] => 11724448 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5064923 [patent_doc_number] => 20070226565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF TESTING SAME' [patent_app_type] => utility [patent_app_number] => 11/683954 [patent_app_country] => US [patent_app_date] => 2007-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11029 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20070226565.pdf [firstpage_image] =>[orig_patent_app_number] => 11683954 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 97025 [patent_doc_number] => 07734975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Semiconductor integrated circuit having built-n self test circuit of logic circuit and embedded device, and design apparatus thereof' [patent_app_type] => utility [patent_app_number] => 11/683759 [patent_app_country] => US [patent_app_date] => 2007-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8477 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/734/07734975.pdf [firstpage_image] =>[orig_patent_app_number] => 11683759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7589350 [patent_doc_number] => 07665000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'Meeting point thread characterization' [patent_app_type] => utility [patent_app_number] => 11/714938 [patent_app_country] => US [patent_app_date] => 2007-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3708 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/665/07665000.pdf [firstpage_image] =>[orig_patent_app_number] => 11714938 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5030035 [patent_doc_number] => 20070271482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'Programmable address space built-in self test (BIST) device and method for fault detection' [patent_app_type] => utility [patent_app_number] => 11/713258 [patent_app_country] => US [patent_app_date] => 2007-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2634 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20070271482.pdf [firstpage_image] =>[orig_patent_app_number] => 11713258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 193012 [patent_doc_number] => 07644339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'Overlapping sub-matrix based LDPC (low density parity check) decoder' [patent_app_type] => utility [patent_app_number] => 11/709078 [patent_app_country] => US [patent_app_date] => 2007-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 14733 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/644/07644339.pdf [firstpage_image] =>[orig_patent_app_number] => 11709078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 66572 [patent_doc_number] => 07765449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-27 [patent_title] => 'Test apparatus that tests a plurality of devices under test having plural memory cells and test method therefor' [patent_app_type] => utility [patent_app_number] => 11/707658 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11782 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/765/07765449.pdf [firstpage_image] =>[orig_patent_app_number] => 11707658 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7532640 [patent_doc_number] => 07844874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-30 [patent_title] => 'Semiconductor integrated circuit device and inspection method therefor' [patent_app_type] => utility [patent_app_number] => 11/704370 [patent_app_country] => US [patent_app_date] => 2007-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 17030 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/844/07844874.pdf [firstpage_image] =>[orig_patent_app_number] => 11704370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5076901 [patent_doc_number] => 20070120125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Semiconductor Integrated Circuit Device and Method of Testing the Same' [patent_app_type] => utility [patent_app_number] => 11/669789 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 53 [patent_no_of_words] => 29162 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20070120125.pdf [firstpage_image] =>[orig_patent_app_number] => 11669789 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 313355 [patent_doc_number] => 07530000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Early detection of storage device degradation' [patent_app_type] => utility [patent_app_number] => 11/669150 [patent_app_country] => US [patent_app_date] => 2007-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3407 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/530/07530000.pdf [firstpage_image] =>[orig_patent_app_number] => 11669150 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4847015 [patent_doc_number] => 20080183423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'SCORING METHOD FOR CORRELATION ANOMALIES' [patent_app_type] => utility [patent_app_number] => 11/668745 [patent_app_country] => US [patent_app_date] => 2007-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3006 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20080183423.pdf [firstpage_image] =>[orig_patent_app_number] => 11668745 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 313349 [patent_doc_number] => 07529994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Analysis apparatus and analysis method' [patent_app_type] => utility [patent_app_number] => 11/657381 [patent_app_country] => US [patent_app_date] => 2007-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4206 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/529/07529994.pdf [firstpage_image] =>[orig_patent_app_number] => 11657381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5161520 [patent_doc_number] => 20070174564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Medium drive and method of generating a defect map for registering positions of defects on a medium' [patent_app_type] => utility [patent_app_number] => 11/654045 [patent_app_country] => US [patent_app_date] => 2007-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6612 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20070174564.pdf [firstpage_image] =>[orig_patent_app_number] => 11654045 [rel_patent_id] =>[rel_patent_doc_number] =>)